Changes

Jump to navigation Jump to search
190 bytes added ,  22:18, 6 November 2010
More CNT bit4 and bit5 info.
Line 32: Line 32:  
|-
 
|-
 
| 4
 
| 4
| SCL hold. When clear SCL is being held low, set when SCL is high. This bit must always be set after writing REG_I2CCNT.
+
| SCL hold. When clear SCL is being held low, set when SCL is high. This bit must always be set(by reading CNT again) after writing REG_I2CCNT. This bit must be set when writing blocks of data(more than 1 byte) with bit0 clear.
 
|-
 
|-
 
| 5
 
| 5
| SCL, toggle this for each loop iteration(in the loop execute the I2C WR code) with max 8 iterations where the loop exits successfully when bit 4 is set.
+
| SCL, toggle this for each loop iteration(in the loop execute the I2C WR code) with max 8 iterations where the loop exits successfully when bit 4 is set. This bit must be set when writing blocks of data(more than 1 byte) with bit0 clear.
 
|-
 
|-
 
| 6
 
| 6

Navigation menu