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DSi XL testpoints (view source)

Revision as of 02:30, 13 August 2023

1,058 bytes added ,  02:30, 13 August 2023
→‎UTL-CPU-01 testpoints: up to 159
Line 647: Line 647:  
|  
 
|  
 
| bottom LCD B.bit3
 
| bottom LCD B.bit3
 +
|-
 +
| TP140
 +
| LDB14
 +
|
 +
| bottom LCD B.bit4
 +
|-
 +
| TP141
 +
| LDB15
 +
|
 +
| bottom LCD B.bit5
 +
|-
 +
| TP142
 +
| VDD5 or VSHD
 +
| 5.0V power rail
 +
| VDD5 and VSHD are the same net
 +
|-
 +
| TP143
 +
| GSP
 +
|
 +
|
 +
|-
 +
| TP144
 +
| VDD5 or VSHD
 +
| 5.0V power rail
 +
| VDD5 and VSHD are the same net
 +
|-
 +
| TP145
 +
| REV
 +
|
 +
|
 +
|-
 +
| TP146
 +
| LS
 +
|
 +
|
 +
|-
 +
| TP147
 +
| SPL
 +
|
 +
|
 +
|-
 +
| TP148
 +
| DCLK
 +
|
 +
| dot clock
 +
|-
 +
| TP149
 +
| CAM_RST
 +
| 1V8?
 +
| camera reset signal
 +
|-
 +
| TP150
 +
| COM1
 +
|
 +
|
 +
|-
 +
! scope="row" colspan="4" | (TP151 doesn't exist)
 +
|-
 +
| TP152
 +
| CAM_D4
 +
| 1V8?
 +
| camera parallell port (conn. thru RA7, 270Ω)
 +
|-
 +
| TP153
 +
| HSYNC
 +
| 1V8?
 +
| horizontal sync/blank (conn. thru R133, 0Ω)
 +
|-
 +
| TP154
 +
| CAM_D3
 +
| 1V8?
 +
| camera parallell port (conn. thru RA6, 270Ω)
 +
|-
 +
| TP155
 +
| VSYNC
 +
| 1V8?
 +
| vertical sync/blank (conn. thru R132, 0Ω)
 +
|-
 +
| TP156
 +
| CKI
 +
| 1V8?
 +
| camera clock something?
 +
|-
 +
| TP157
 +
| CAM_D2
 +
| 1V8?
 +
| camera parallell port (conn. thru RA6, 270Ω)
 +
|-
 +
| TP158
 +
| CAM_D7
 +
| 1V8?
 +
| camera parallell port (conn. thru RA7, 270Ω)
 +
|-
 +
| TP159
 +
| CAM_D1
 +
| 1V8?
 +
| camera parallell port (conn. thru RA6, 270Ω)
 
|-
 
|-
 
! scope="row" colspan="4" | <work in progress>
 
! scope="row" colspan="4" | <work in progress>
PoroCYon
75

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Retrieved from "https://dsibrew.org/wiki/Special:MobileDiff/2099871"

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