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Line 134: − '''400481Ch - SD_IRQ_STATUS0-1 - Interrupt Status (R/ack)'''<br>+ − '''4004A1Ch - SDIO_IRQ_STATUS0-1 - Interrupt Status (R/ack)'''<br>+ − '''4004820h - SD_IRQ_MASK0-1 - Interrupt Mask (R/W)'''<br>+ − '''4004A20h - SDIO_IRQ_MASK0-1 - Interrupt Mask (R/W)'''<br>+ − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − − − − Acknowledge by STAT=0, or by MASK=1 (uh, really?), or by soft reset (SRST=0) or − hard reset. − + − '''4004900h - SD_DATA32_IRQ'''<br> − '''4004B00h - SDIO_DATA32_IRQ'''<br> − + − + − + − + − + − + − + − + − + − + − − − − '''400482Ch - SD_ERROR_DETAIL_STATUS0-1 - Error Detail Status'''<br>+ − '''4004A2Ch - SDIO_ERROR_DETAIL_STATUS0-1 - Error Detail Status'''<br> Line 208:
Line 197: − + Line 222:
Line 211: − + − + − − − − '''4004A36h - DSi: 0000 - SDCTL_CARD_INTERRUPT_CONTROL'''<br> − This does NOT seem to be implemented as described below on DSi. − 4004A36h does seem to behave more like 4004836h, see there. − 15-13 ? Unknown (zero on DSi) − 12 CINT0 SDIO Interrupt Flag (0=none, 1=irq) (/IRQ aka Data1 pin) − 11-9 ? Unknown (zero on DSi) − 8 CIMSK0 SDIO Interrupt Mask (0=enable, 1=disable) (/IRQ aka Data1 pin) − 7-0 ? Unknown (zero on DSi) − Acknowledge by writing CINT0=0, or CIMSK0=1, or hard reset (unlike as for other − SD/MMC interrupts, soft reset does not acknowlege this interrupt type?).
→DSi SD/MMC I/O Ports: Interrupt/Status
== DSi SD/MMC I/O Ports: Interrupt/Status ==
== DSi SD/MMC I/O Ports: Interrupt/Status ==
===400481Ch/4004A1Ch - SD_IRQ_STATUS0-1 - Interrupt Status (R/ack)===
===4004820h/4004A20h - SD_IRQ_MASK0-1 - Interrupt Mask (R/W)===
The IRQ_STATUS registers contain acknowledge-able IRQ Flags (those bits that that are maskable in IRQ_MASK register), as well as static read-only status bits without IRQ function (eg. WRPROTECT).
*IRQ Flags/Write (0=Acknowledge, 1=No change)
The IRQ_STATUS registers contain acknowledge-able IRQ Flags (those bits that
*IRQ Flags/Read (0=No IRQ, 1=IRQ)
that are maskable in IRQ_MASK register), as well as static read-only status
*IRQ Mask (0=Enable, 1=Disable) (8B7F031Dh when all IRQs disabled)
bits without IRQ function (eg. WRPROTECT).
Bit Stat Mask Function
* IRQ Flags/Write (0=Acknowledge, 1=No change)
0 SREP MREP CMDRESPEND (response end) (or R1b: busy end)
* IRQ Flags/Read (0=No IRQ, 1=IRQ)
1 0 0 Unknown/unused (always 0)
* IRQ Mask (0=Enable, 1=Disable) (8B7F031Dh when all IRQs disabled)
2 SRWA MRWA DATAEND (set after (last) data block end)
Bit Stat Mask Function
3 SCOT MCOT CARD_REMOVE (0=No event, 1=Is/was newly ejected) ;\
0 SREP MREP CMDRESPEND (response end) (or R1b: busy end)
4 SCIN MCIN CARD_INSERT (0=No event, 1=Is/was newly inserted) ; SD
1 0 0 Unknown/unused (always 0)
5 undoc 0 SIGSTATE (0=Ejected, 1=Inserted) (SDIO: always 1) ; Slot
2 SRWA MRWA DATAEND (is NOT set? after data read/write end bit)
6 0 0 Unknown/unused (always 0) ; Sw's
3 SCOT MCOT CARD_REMOVE (0=No event, 1=Is/was newly ejected) ;\DSi
7 undoc 0 WRPROTECT (0=Locked/Ejected, 1=Unlocked/HalfEjected);/
4 SCIN MCIN CARD_INSERT (0=No event, 1=Is/was newly inserted) ; SD
8 undoc undoc CARD_REMOVE_A (0=No event, 1=High-to-Low occurred) ;\SD
5 undoc 0 SIGSTATE (0=Ejected, 1=Inserted) (SDIO: always 1) ; Card
9 undoc undoc CARD_INSERT_A (0=No event, 1=Low-to-High óccurred) ; Slot
6 0 0 Unknown/unused (always 0) ; Slot
10 undoc 0 SIGSTATE_A (usually 1=High) ;also as so for SDIO ;/Data3
7 undoc 0 WRPROTECT (0=Locked/Ejected, 1=Unlocked/HalfEjected);/
11 0 0 Unknown/unused (always 0)
8 undoc undoc CARD_REMOVE_A (always 0) ;\maybe fixed state for
12 0 0 Unknown/unused (always 0)
9 undoc undoc CARD_INSERT_A (always 0) ; DSi's onboard eMMC chip
13 0 0 Unknown/unused (always 0)
10 undoc 0 SIGSTATE_A (always 1) ;/(also fixed as so for SDIO)
14 0 0 Unknown/unused (always 0)
11 0 0 Unknown/unused (always 0)
15 0 0 Unknown/unused (always 0)
12 0 0 Unknown/unused (always 0)
16 SCIX MCIX CMD_IDX_ERR Bad CMD-index in response (RCMDE,SCMDE)
13 0 0 Unknown/unused (always 0)
17 SCRC MCRC CRCFAIL CRC response error (WCRCE,RCRCE,SCRCE,CCRCE)
14 0 0 Unknown/unused (always 0)
18 SEND MEND STOPBIT_ERR End bit error (WEBER,REBER,SEBER,CEBER)
15 0 0 Unknown/unused (always 0)
19 SDTO MDTO DATATIMEOUT Data Timeout (NRCS,NWCS,KBSY)
16 SCIX MCIX CMD_IDX_ERR Bad CMD-index in response (RCMDE,SCMDE)
20 SFOF MFOF RXOVERFLOW HOST tried write full
17 SCRC MCRC CRCFAIL CRC response error (WCRCE,RCRCE,SCRCE,CCRCE)
21 SFUF MFUF TXUNDERRUN HOST tried read empty
18 SEND MEND STOPBIT_ERR End bit error (WEBER,REBER,SEBER,CEBER)
22 SCTO MCTO CMDTIMEOUT Response start-bit timeout (NRS,NSR)
19 SDTO MDTO DATATIMEOUT Data Timeout (NRCS,NWCS,KBSY)
23 1 ? 0 Unknown/undoc (usually set?)
20 SFOF MFOF RXOVERFLOW HOST tried write full
24 SBRE MBRE RXRDY (fifo not empty) (request data read)
21 SFUF MFUF TXUNDERRUN HOST tried read empty
25 SBWE MBWE TXRQ (datafifoempty?) (request data write)
22 SCTO MCTO CMDTIMEOUT Response start-bit timeout (NRS,NSR)
26 0 0 Unknown/unused (always 0)
23 1 ? 0 Unknown/undoc (usually set?)
27 undoc undoc Unknown/undoc (bit27 is mask-able in IRQ_MASK)
24 SBRE MBRE RXRDY (fifo not empty) (request data read)
28 0 0 Unknown/unused (always 0)
25 SBWE MBWE TXRQ (datafifoempty?) (request data write)
29 undoc 0 CMD_READY? (inverse of BUSY?) (unlike toshiba ILFSL/IFSMSK)
26 0 0 Unknown/unused (always 0)
30 undoc 0 CMD_BUSY
27 undoc undoc Unknown/undoc (bit27 is mask-able in IRQ_MASK)
31 ILA IMSK Illegal Command Access (old CMD still busy, or wrong NTDT)
28 0 0 Unknown/unused (always 0)
Normally, IRQs should be acknowledged by writing "FLAGS=NOT X", whilst the firmware is using an unstable "FLAGS=FLAGS AND NOT X" read-modify-write function (accidentally acknowledging any IRQs that have newly occurred during that operation).
29 1 ? 0 Unknown/undoc (usually set?) (unlike toshiba ILFSL/IFSMSK)
30 undoc 0 CMD_BUSY
31 ILA IMSK Illegal Command Access (old CMD still busy, or wrong NTDT)
===4004900h/4004B00h - SD_DATA32_IRQ===
15-13 Unknown/unused (appears to be always zero)
15-13 Unknown/unused (appears to be always zero)
12 Unknown (paired with bit9) (can be set) IRQ enable ?! (R/W?)
12 DATA32_BUSY IRQ Enable (0=Disable, 1=Enable) (R/W)
11 Unknown (paired with bit8) (can be set) IRQ enable ?! (R/W?)
11 DATA32_RXRDY IRQ Enable (0=Disable, 1=Enable) (R/W)
10 Unknown (read=0) write: (0=No change, 1=Clear Bit8,9) ? (W?)
10 DATA32 Abort/Flush FIFO? (0=No change, 1=Clear Bit8,9) (W)
9 Unknown (paired with bit12) (automatically cleared after...) (R?)
9 DATA32_BUSY IRQ Flag (auto cleared after...) (R)
8 Unknown (paired with bit11) (R?)
8 DATA32_RXRDY IRQ Flag (auto cleared after...) (R)
7-2 Unknown (0)
7-2 Unknown/unused (appears to be always zero)
1 Unknown (can be set) (autoclear bit8,9 on xfer end?) (R/W?)
1 Select 16bit/32bit Data Mode (0=DATA16, 1=DATA32, see 40048D8h) (R/W)
0 Unknown (0)
0 Unknown/unused (appears to be always zero)
Can be 1A02h, but changes to 1802h after reading from somewhere (maybe from
Can be 1A02h, but changes to 1802h after reading from somewhere (maybe from DATA32_FIFO?).<br>
DATA32_FIFO?).<br>
Bit8,9 are extra IRQ flags, the flags get set ONLY in DATA32 mode (not in DATA16 mode).
Bit8,9 seem to be whatever extra IRQ flags, the flags get set ONLY in DATA32
mode (not in DATA16 mode).
===400482Ch/4004A2Ch - SD_ERROR_DETAIL_STATUS0-1 - Error Detail Status===
31-23 ? Unknown/unused/undoc
31-23 ? Unknown/unused/undoc
22 KBSY Timeout for CRC status busy timeout ;\STAT.19
22 KBSY Timeout for CRC status busy timeout ;\STAT.19
16 NCR Response timeout for non-auto-issued CMD's ;/(SCTO)
16 NCR Response timeout for non-auto-issued CMD's ;/(SCTO)
15-14 ? Unknown/unused/undoc
15-14 ? Unknown/unused/undoc
13 ?? Unknown/undoc (bit13 can be nonzero on DSi!)
13 ?? Unknown/undoc (bit13 can be nonzero on DSi!) (always 1?) (R?)
12 ? Unknown/unused/undoc
12 ? Unknown/unused/undoc
11 WCRCE CRC error for Write CRC status for a write command ;\
11 WCRCE CRC error for Write CRC status for a write command ;\
Unknown if/when/how the error bits can be reset/acknowledged.<br>
Unknown if/when/how the error bits can be reset/acknowledged.<br>
Note: CMD12 is STOP_TRANSMISSION (maybe sent after BLK_COUNT?).<br>
Note: CMD12 is STOP_TRANSMISSION (maybe sent after BLK_COUNT?).<br>
The four "auto-issued CMD12" bits exist for SD registers only (not SDIO).
The four "auto-issued CMD12" bits exist for SD registers only (not SDIO).<br>
SCMDE is probably in bit1 (though, official specs say bit0, which would be same
SCMDE is probably in bit1 (though, official specs say bit0, which would be same as RCMDE).
as RCMDE).
== DSi SD/MMC I/O Ports: Control ==
== DSi SD/MMC I/O Ports: Control ==