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Line 65:
Line 65: − '''4004800h - SD_CMD - Command and Response/Data Type (R/W)'''<br>+ − '''4004A00h - SDIO_CMD - Command and Response/Data Type (R/W)'''<br> Line 76:
Line 75: − + − + − − − − − − − + − '''4004804h - SD_CMD_PARAM0-1 - Argument (32bit, 2 halfwords) (R/W)'''<br> − '''4004A04h - SDIO_CMD_PARAM0-1 - Argument (32bit, 2 halfwords) (R/W)'''<br> − + − − − '''400480Ch - SD_RESPONSE0-7 - Response (128bit, 8 halfwords) (R)'''<br>+ − '''4004A0Ch - SDIO_RESPONSE0-7 - Response (128bit, 8 halfwords) (R)'''<br> − + − + − + − − − − '''DATA16 vs DATA32'''<br>+ − + − + − − − − − − '''40048D8h - SD_DATA_CTL'''<br>+ − '''4004AD8h - SDIO_DATA_CTL'''<br> − + − + − + − + − + − + + + + + + − '''400480Ah - SD_DATA16_BLK_COUNT - "Transfer Sector Count" (R/W)'''<br>+ − '''4004908h - SD_DATA32_BLK_COUNT (R/W)'''<br>+ − '''4004A0Ah - SDIO_DATA16_BLK_COUNT - "Transfer Block Count" (R/W)'''<br> − '''4004B08h - SDIO_DATA32_BLK_COUNT (R/W)'''<br> − 15-0 Number of Data Blocks for multiple read/write commands − Can be max FFFFh. The DATA32_BLK_COUNT value decreases after reading from − somewhere (maybe from DATA32_FIFO?). − − − '''4004826h - SD_DATA16_BLK_LEN - Memory Card Transfer Data Length (R/W)'''<br> − '''4004904h - SD_DATA32_BLK_LEN (R/W)'''<br> − '''4004A26h - SDIO_DATA16_BLK_LEN - Card Transfer Data Length (R/W)'''<br> − '''4004B04h - SDIO_DATA32_BLK_LEN (R/W)'''<br> − + − − − + − '''4004830h - SD_DATA16_FIFO - Data Port (SD_FIFO?)'''<br>+ − '''400490Ch - SD_DATA32_FIFO'''<br>+ − '''4004A30h - SDIO_DATA16_FIFO - Data Port (SD_FIFO?)'''<br> − '''4004B0Ch - SDIO_DATA32_FIFO'''<br> − − + −
→DSi SD/MMC I/O Ports: Command/Param/Response/Data
== DSi SD/MMC I/O Ports: Command/Param/Response/Data ==
== DSi SD/MMC I/O Ports: Command/Param/Response/Data ==
===4004800h/4004A00h - SD_CMD - Command and Response/Data Type (R/W)===
15 undoc Unknown/undoc (read/write-able)
15 undoc Unknown/undoc (read/write-able)
14 undoc Security Cmd (0=Normal, 1=Whatever/Security) (sdio?)
14 undoc Security Cmd (0=Normal, 1=Whatever/Security) (sdio?)
7-6 CMD1-0 Command Type (0=CMD, 1=ACMD, 2..3=unknown, maybe GEN WR/RD?)
7-6 CMD1-0 Command Type (0=CMD, 1=ACMD, 2..3=unknown, maybe GEN WR/RD?)
5-0 CIX Command Index (0..3Fh, command index)
5-0 CIX Command Index (0..3Fh, command index)
Invalid values can cause ILA error (particulary on setting NTDT for CMD12, or
Invalid values can cause ILA error (particulary on setting NTDT for CMD12, or for CMD's Response=None). ILA error will also occur if an old CMD is still busy.<br>
for CMD's Response=None). ILA error will also occur if an old CMD is still
DSi software is always writing just ZERO to bit11-6 though? Maybe the hardware does automatically know which SD/MMC CMDs and ACMDs have data? Or maybe data is always automatically transferred when receiving a data-startbit, or when writing to data register - and bits like NTDT would be needed only for things like proper data timeout handling?
busy.
DSi software is always writing just ZERO to bit11-6 though? Maybe the hardware
does automatically know which SD/MMC CMDs and ACMDs have data? Or maybe data is
always automatically transferred when receiving a data-startbit, or when
writing to data register - and bits like NTDT would be needed only for things
like proper data timeout handling?
===4004804h/4004A04h - SD_CMD_PARAM0-1 - Argument (32bit, 2 halfwords) (R/W)===
31-0 Parameter value for CMD
31-0 Parameter value for CMD
The parameter value should be written <before> sending the command via
The parameter value should be written <before> sending the command via SD_CMD/SDIO_CMD.
SD_CMD/SDIO_CMD.
===400480Ch/4004A0Ch - SD_RESPONSE0-7 - Response (128bit, 8 halfwords) (R)===
After sending a command, wait for the CMDRESPEND bit (IRQ_STATUS.bit0) to get
After sending a command, wait for the CMDRESPEND bit (IRQ_STATUS.bit0) to get
set, then read the RESPONSE (if the command does have any response).
set, then read the RESPONSE (if the command does have any response).
For normal 32bit responses:
For normal 32bit responses:
31-0 Response
31-0 Response
127-32 Older Responses
127-32 Older Responses
For CID/CSD responses:
For CID/CSD responses:
119-0 120bit Response
119-0 120bit Response
127-120 Zero (always?)
127-120 Zero (always?)
Seems to be left-shifted when receiving response bits. So, for 32bit responses,
Seems to be left-shifted when receiving response bits. So, for 32bit responses, bit0-31 would contain the current response, and bit32-127 would contain older responses.
bit0-31 would contain the current response, and bit32-127 would contain older
responses.
===DATA16 vs DATA32===
Data can be transferred in 16bit or 32bit units (as selected in DATA_CTL.bit1).
Data can be transferred in 16bit or 32bit units (as selected in DATA_CTL.bit1 and DATA32_IRQ.bit1). There are separate data, block len, and block count registers for 16bit and 32bit mode (that's probably due to some odd patchwork, where the manufacturer has added 32bit support to the original 16bit chip design).<br>
There are separate data, block len, and block count registers for 16bit and
Naturally, a 32bit transfer is faster than two 16bit transfers. Nethertheless, the DSi firmware does use both 32bit and 16bit mode once and then; 32bit mode is required for NDMA transfers (which don't support 16bit).
32bit mode (that's probably due to some odd patchwork, where the manufacturer
has added 32bit support to the original 16bit chip design).
Naturally, a 32bit transfer is faster than two 16bit transfers. Nethertheless,
the DSi firmware does use both 32bit and 16bit mode once and then; 32bit mode
is required for NDMA transfers (which don't support 16bit).
===40048D8h/4004AD8h - SD_DATA_CTL===
15-13 Unknown (usually 0)
15-13 Unknown (usually 0)
12 Unknown (usually 1) (R?)
12 Unknown (usually 1) (R?)
11-6 Unknown (usually 0)
11-6 Unknown (usually 0)
5 Unknown (R/W?) (R/W?)
5 Unknown (read/write-able) (usually 0) (R/W)
4 Unknown (usually 1) (R?)
4 Unknown (usually 1) (R?)
3-2 Unknown (usually 0)
3-2 Unknown (usually 0)
1 Select 16bit/32bit Data Mode (0=DATA16, 1=DATA32) (R/W?)
1 Select 16bit/32bit Data Mode (0=DATA16, 1=DATA32, see 4004900h) (R/W)
0 Unknown (usually 0)
0 Unknown (usually 0)
Known written values are 0000h and 0002h. However, known read values are 1010h
Known written values are 0000h and 0002h. However, known read values are 1010h and 1012h.<br>
and 1012h.
DATA32 mode requires setting both 40048D8h.bit1 and 4004900h.bit1. For DATA16 mode, both bits should be zero (though DATA16 seems to be also working the same way when only either of the bits is zero).
===400480Ah/4004A0Ah - SD_DATA16_BLK_COUNT - "Transfer Block Count" (R/W)===
===4004908h/4004B08h - SD_DATA32_BLK_COUNT (R/W)===
15-0 Number of Data Blocks for multiple read/write commands (0..FFFFh)
In Data32 mode, DATA32_BLK_COUNT is decremented after each block (except after the last block, where it stays at 0001h instead of getting zero). In Data16 mode, SD_DATA16_BLK_COUNT doesn't decrease (instead, there must be some hidden internal counter register).<br>
If enabled in STOP_INTERNAL_ACTION.bit8, then the hardware will be automatically sending STOP_TRANSMISSION (CMD12) after the last block (otherwise the decrement occurs as described above, but the hardware keeps transferring blocks infinitely).
===4004826h/4004A26h - SD_DATA16_BLK_LEN - Transfer Data Length (R/W)===
===4004904h/4004B04h - SD_DATA32_BLK_LEN (R/W)===
15-10 Unknown/unused (appears to be always zero)
15-10 Unknown/unused (appears to be always zero)
9-0 Data Block Length in bytes (for DATA16: clipped to max 0200h by hw)
9-0 Data Block Length in bytes (for DATA16: clipped to max 0200h by hw)
Should be usually 0200h (for 512-byte SD/MMC memory blocks). Other values may
Should be usually 0200h (for 512-byte SD/MMC memory blocks). Other values may be needed for SDIO functions, or when accessing SSR/SCR/PWD registers via data transfers.<br>
be needed for SDIO functions, or when accessing SSR/SCR/PWD registers via data
transfers.
DATA32_BLK_LEN can be max 3FFh (unlike DATA16_BLK_LEN which is clipped to
DATA32_BLK_LEN can be max 3FFh (unlike DATA16_BLK_LEN which is clipped to
max=200h by hardware).
max=200h by hardware).
===4004830h/4004A30h - SD_DATA16_FIFO - Data Port (SD_FIFO?)===
===400490Ch/4004B0Ch - SD_DATA32_FIFO===
For Data16:
For Data16:
15-0 Data (16bit) (...or could it be accessed as 32bit, too?)
15-0 Data (16bit) (...or could it be accessed as 32bit, too?)
For Data32:
For Data32:
31-0 Data (32bit) (...or could it be accessed as 16bit, too?)
31-0 Data (32bit) (...or could it be accessed as 16bit, too?)
Transfer data here (read after RXRDY gets set, or write after TXRQ gets set).
Transfer data here (read after RXRDY gets set, or write after TXRQ gets set).
FIFO size is unknown (if there's any FIFO behind it).
FIFO size is unknown (if there's any FIFO behind it).
== DSi SD/MMC I/O Ports: Interrupt/Status ==
== DSi SD/MMC I/O Ports: Interrupt/Status ==