Changes

2,160 bytes added ,  22:49, 1 September 2023
Xtensa JTAG stuff (yeah)
Line 24: Line 24:  
=== DWM-W015 ===
 
=== DWM-W015 ===
   −
http://www.flickr.com/photos/micahdowty/3846960965/sizes/o/in/photostream/
+
[http://www.flickr.com/photos/micahdowty/3846960965/sizes/o/in/photostream/ Image source]
 +
 
 +
[[Image:Dwm-w015-scanlime.jpg|800px]]
    
=== DWM-W015A ===
 
=== DWM-W015A ===
Line 35: Line 37:     
[[Image:Dwm-w024.jpg|800px]]
 
[[Image:Dwm-w024.jpg|800px]]
 +
 +
== Debugging the Ath6k Xtensa CPU ==
 +
 +
In case you want to run your own code on it (and subsequently need to debug it), the Atheros chip has two debug facilities: UART and JTAG. UART is a simple serial connection for printf-debugging, while JTAG can be used for single-stepping, breakpoints, etc.
 +
 +
'''NOTE THAT BOTH UART AND JTAG USE 1.8V LOGIC LEVELS. DO NOT DRIVE WITH 3.3 OR 5.0 V!!!'''
 +
 +
=== UART ===
 +
 +
Serial communication on the Xtensa side can be done as [https://problemkaputt.de/gbatek-dsi-atheros-wifi-internal-i-o-00c000h-serial-uart-hw2-hw4-hw6.htm described in GBATEK]. On the DWM-W015, the UART testpoints appear on the bottom side of the PCB, near the edge (see below). On the DWM-W024, RX and TX are probably one of the four testpoints on the top side (see above).
 +
 +
[[Image:Dwm-w015-bottom-marked.jpg|400px]]
 +
 +
=== JTAG ===
 +
 +
The four primary JTAG pins are exposed on the connector to the main board. However, the AR6002 has two extra pins that control JTAG functionality: JTAG_nRST and EJTAG_RST. They are marked in the image below, and they work as follows:
 +
 +
* '''JTAG_nRST''' resets the CPU core when pulled low. Some debuggers use this signal.
 +
* '''EJTAG_RST''' is latched on chip powerup. If high, after a 'system' reset (read: the nWIFI_RST on the connector is pulled low), the Xtensa CPU is held at reset until JTAG_nRST is brought high. If EJTAG_RST is low, nothing special happens.
 +
 +
Thus, if your debugger has a JTAG_nRST signal (and you want to use it), pull EJTAG_RST to VDD18, and connect JTAG_nRST to your debugger. Otherwise, pull EJTAG_RST to ground (or leave it floating as-is, it probably has an internal pulldown).
 +
 +
As debugger, OpenOCD (or its fork for the ESP32) and any JTAG dongle compatible with it should work. '''Note that all JTAG communications use 1.8V! Using a higher voltage will kill the AR6002!'''
 +
 +
[[Image:Dwm-w015-top-marked.jpg|400px]]
 +
 +
=== DWM-W024 testpoints ===
 +
 +
The DWM-W024 has four testpoints with currently-unknown functionality. These are probably UART TX, UART RX, JTAG_nRST, and EJTAG_RST. However, which testpoint is which signal is not yet known.
    
== Documents and external links ==
 
== Documents and external links ==
75

edits