Changes

===4004828h/4004A28h - SD_CARD_OPTION - Card Option Setup===

===4004828h/4004A28h - SD_CARD_OPTION - Card Option Setup===

   15       Bus Width (0=4bit, 1=1bit)                       (R/W)

   15   undoc Bus Width (0=4bit, 1=1bit)                                   (R/W)

   14       Unknown (usually set)                             (R?)

   14   undoc Unknown (usually set)                                       (R?)

   13-9     Unknown/unused (appears to be always zero)

   13-9 0    Unknown/unused (appears to be always zero)

   8         Unknown (firmware toggles this after CLK change?) (W?)

   8   undoc Unknown (firmware tries to toggle this after CLK change?)   (W?)

   7-4       Unknown, maybe some 4bit timing/timeout value    (R/W)

   7-4 RTO  Data start/busy timout (2000h SHL 0..14, or 15=100h SDCLK's) (R/W)

   0-3       Unknown, maybe another 4bit timing/timeout value  (R/W)

   0-3 TO?  Unknown (another timeout, maybe for SDIO? in 32KHz units?)  (R/W)

Among others, this register should contain a 4bit timeout setting, "RTO[3:0] for SD (aka TO[3:0] for SDIO) timeout period for data start/busy bits, in the form of a multiple number of the SDCLK period."<br>

Among others, this register should contain a 4bit timeout setting, "RTO[3:0]

Unknown which "multiple numbers" that's referring to (probably some exponential/table values).<br>

for SD (aka TO[3:0] for SDIO) timeout period for data start/busy bits, in the

form of a multiple number of the SDCLK period." Unknown which "multiple

numbers" that's referring to (probably some exponential/table values).

Settings spotted on DSi are 40E0h,40EEh.

Settings spotted on DSi are 40E0h,40EEh.