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Line 67: − + − + − + − DSi software is always writing just ZERO to bit11-6 though? Maybe the hardware does automatically know which SD/MMC CMDs and ACMDs have data? Or maybe data is always automatically transferred when receiving a data-startbit, or when writing to data register - and bits like NTDT would be needed only for things like proper data timeout handling?+ + + + Line 164:
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Line 192: − + − + − + + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − Unknown if/when/how the error bits can be reset/acknowledged.<br>+ − + − + − + Line 218:
Line 222: − + − + − 8 Unknown (write: should be 0, read: usually 1 for SDIO) (R?) Line 226:
Line 229: − + − + − + − + − + − + − + − + + + Line 266:
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SD/MMC/SDIO Registers (view source)
Revision as of 14:29, 2 September 2015
, 14:29, 2 September 2015→40048FAh - Can be 0004h..0007h (nonzero, unlike SDIO) (RESERVED6)
===4004800h/4004A00h - SD_CMD - Command and Response/Data Type (R/W)===
===4004800h/4004A00h - SD_CMD - Command and Response/Data Type (R/W)===
15 undoc Unknown/undoc (read/write-able)
15 undoc Unknown/undoc (read/write-able)
14 undoc Security Cmd (0=Normal, 1=Whatever/Security) (sdio?)
14 undoc Security Cmd? (0=Normal, 1=Whatever/Security?) (sdio?)
13 undoc Data Length (0=Single Block, 1=Multiple Blocks)
13 undoc Data Length (0=Single Block, 1=Multiple Blocks)
12 undoc Data Direction (0=Write, 1=Read)
12 undoc Data Direction (0=Write, 1=Read)
11 NTDT Data Transfer (0=No data, 1=With data)
11 NTDT Data Transfer (0=No data, 1=With data)
10-8 REP2-0 Response Type (0..2=Unknown/Reserved, 3=None, 4=48bit,
10-8 REP2-0 Response Type (0=Auto, 1..2=Unknown/Reserved, 3=None, 4=48bit,
5=48bit+Busy, 6=136bit, 7=48bitOcrWithoutCRC7)
5=48bit+Busy, 6=136bit, 7=48bitOcrWithoutCRC7)
7-6 CMD1-0 Command Type (0=CMD, 1=ACMD, 2..3=unknown, maybe GEN WR/RD?)
7-6 CMD1-0 Command Type (0=CMD, 1=ACMD, 2..3=unknown, maybe GEN WR/RD?)
5-0 CIX Command Index (0..3Fh, command index)
5-0 CIX Command Index (0..3Fh, command index)
Invalid values can cause ILA error (particulary on setting NTDT for CMD12, or for CMD's Response=None). ILA error will also occur if an old CMD is still busy.<br>
Setting Command Type to "ACMD" is automatically sending an APP_CMD prefix prior to the command number. For Multiple Blocks, the hardware supports automatically sending STOP_TRANSMISSION after the last block.<br>
DSi software is usually setting Response Type to "Auto", which is causing the hardware to use the correct response/data type for standard SD/MMC commands (bit11-13 are ignored/should be zero when using "Auto"; and maybe same for bit14-15?).<br>
One exception is that the DSi firmware isn't using "Auto" for SDIO commands (maybe the hardware isn't aware of them; or it's unable to distinguish between read/write direction of CMD53, which would require examining the command's PARAM bits).<br>
There might be subtle differences between some SD and MMC commands, unknown if/how "Auto" is working in that cases; unknown if there's a SD-or-MMC mode select bit for that purpose in some configuration register.<br>
Invalid values can cause ILA error (particulary on setting NTDT for CMD12, or for CMD's Response=None). ILA error will also occur if an old CMD is still busy.
===4004804h/4004A04h - SD_CMD_PARAM0-1 - Argument (32bit, 2 halfwords) (R/W)===
===4004804h/4004A04h - SD_CMD_PARAM0-1 - Argument (32bit, 2 halfwords) (R/W)===
21 SFUF MFUF TXUNDERRUN HOST tried read empty
21 SFUF MFUF TXUNDERRUN HOST tried read empty
22 SCTO MCTO CMDTIMEOUT Response start-bit timeout (NRS,NSR)
22 SCTO MCTO CMDTIMEOUT Response start-bit timeout (NRS,NSR)
23 1 ? 0 Unknown/undoc (usually set?)
23 ??? 0 Unknown/undoc (usually set) (zero after sending TX data?)
24 SBRE MBRE RXRDY (fifo not empty) (request data read)
24 SBRE MBRE RXRDY (fifo not empty) (request data read)
25 SBWE MBWE TXRQ (datafifoempty?) (request data write)
25 SBWE MBWE TXRQ (datafifoempty?) (request data write)
===400482Ch/4004A2Ch - SD_ERROR_DETAIL_STATUS0-1 - Error Detail Status===
===400482Ch/4004A2Ch - SD_ERROR_DETAIL_STATUS0-1 - Error Detail Status===
31-23 ? Unknown/unused/undoc
This register contains extra info about the error bits in SD_IRQ_STATUS. The error bits (except bit13/always set) are automatically cleared when sending a new command by writing to SD_CMD.
22 KBSY Timeout for CRC status busy timeout ;\STAT.19
31-23 0 Unknown/unused (always zero)
21 NWCS Timeout for CRC status timeout ; (SDTO)
22 KBSY Timeout for CRC status busy ;\STAT.19
21 NWCS Timeout for CRC status (can occur for Data Write) ; (SDTO)
20 NRCS Timeout for Data start-bit, or for Post Data Busy ;/
20 NRCS Timeout for Data start-bit, or for Post Data Busy ;/
19-18 ? Unknown/unused/undoc
19-18 0 Unknown/unused (always zero)
17 NRS Response timeout for auto-issued CMD12 ;\STAT.22
17 NRS Response Timeout for auto-issued CMD12 ;\STAT.22
16 NCR Response timeout for non-auto-issued CMD's ;/(SCTO)
16 NCR Response Timeout for non-auto-issued CMD's ;/(SCTO)
15-14 ? Unknown/unused/undoc
15-14 0 Unknown/unused (always zero)
13 ?? Unknown/undoc (bit13 can be nonzero on DSi!) (always 1?) (R?)
13 undoc Unknown/undoc (always 1) ;-Always 1
12 ? Unknown/unused/undoc
12 0 Unknown/unused (always zero)
11 WCRCE CRC error for Write CRC status for a write command ;\
11 WCRCE CRC error for Write CRC status for a write command ;\
10 RCRCE CRC error for read data ; STAT.17
10 RCRCE CRC error for Read Data ; STAT.17
9 SCRCE CRC error for a response for auto-issued CMD12 ; (SCRC)
9 SCRCE CRC error for a Response for auto-issued CMD12 ; (SCRC)
8 CCRCE CRC error for a response for non-auto-issued CMD's ;/
8 CCRCE CRC error for a Response for non-auto-issued CMD's ;/
5 WEBER End bit error for Write CRC status ;\
5 WEBER End bit error for Write CRC status ;\
4 REBER End bit error for read data ; STAT.18
4 REBER End bit error for Read Data ; STAT.18
3 SEBER End bit error for response for auto-issued CMD12 ; (SEND)
3 SEBER End bit error for Response for auto-issued CMD12 ; (SEND)
2 CEBER End bit error for response for non-auto-issued CMD's ;/
2 CEBER End bit error for Response for non-auto-issued CMD's ;/
1? SCMDE Bad CMD-index in response of auto-issued CMD12 ;\STAT.16
1? SCMDE Bad CMD-index in Response of auto-issued CMD12 ;\STAT.16
0 RCMDE Bad CMD-index in response of non-auto-issued CMD's ;/(SCIX)
0 RCMDE Bad CMD-index in Response of non-auto-issued CMD's ;/(SCIX)
Note: CMD12 is STOP_TRANSMISSION (automatically sent after BLK_COUNT blocks).<br>
Note: CMD12 is STOP_TRANSMISSION (maybe sent after BLK_COUNT?).<br>
The four "auto-issued CMD12" bits exist for SD registers only (not for SDIO, going by old toshiba datasheets; which may be wrong).
The four "auto-issued CMD12" bits exist for SD registers only (not SDIO).<br>
SCMDE is probably in bit1 (though, official specs say bit0, which would be same as RCMDE).<br>
SCMDE is probably in bit1 (though, official specs say bit0, which would be same as RCMDE).
Some error bits can be intentionally provoked: Bit8=1 when programming the controller to expect GET_STATUS to return a 136bit response. Bit16=1 when sending GET_CID in "tran" state. Bit20=1 when sending GET_STATUS configured to expect a data/read reply. Bit21=1 when sending GET_STATUS configured to expect a data/write block (and with actually sending a data block to it).
== DSi SD/MMC I/O Ports: Control Registers ==
== DSi SD/MMC I/O Ports: Control Registers ==
===4004802h/4004A02h - SD_CARD_PORT_SELECT===
===4004802h/4004A02h - SD_CARD_PORT_SELECT===
15-11 Unknown/unused (appears to be always zero)
15-11 Unknown/unused (appears to be always zero)
10 Unknown (write: should be 1, read: usually/always 0) (W?)
10 Unknown (should be set on writing) (reads as zero) (W)
9 Unknown (write: should be 0, read: usually 1 for SD) (R?)
9-8 Unknown (Always 2 for SD/4004802h, always 1 for SDIO/4004A02h) (R)
7-4 Unknown/unused (appears to be always zero)
7-4 Unknown/unused (appears to be always zero)
3-1 Unknown (R/W)
3-1 Unknown (R/W)
===4004828h/4004A28h - SD_CARD_OPTION - Card Option Setup===
===4004828h/4004A28h - SD_CARD_OPTION - Card Option Setup===
15 Bus Width (0=4bit, 1=1bit) (R/W)
15 undoc Bus Width (0=4bit, 1=1bit) (R/W)
14 Unknown (usually set) (R?)
14 undoc Unknown (usually set) (R?)
13-9 Unknown/unused (appears to be always zero)
13-9 0 Unknown/unused (appears to be always zero)
8 Unknown (firmware toggles this after CLK change?) (W?)
8 undoc Unknown (firmware tries to toggle this after CLK change?) (W?)
7-4 Unknown, maybe some 4bit timing/timeout value (R/W)
7-4 RTO Data start/busy timout (2000h SHL 0..14, or 15=100h SDCLK's) (R/W)
0-3 Unknown, maybe another 4bit timing/timeout value (R/W)
0-3 TO? Unknown (another timeout, maybe for SDIO? in 32KHz units?) (R/W)
Among others, this register should contain a 4bit timeout setting, "RTO[3:0] for SD (aka TO[3:0] for SDIO) timeout period for data start/busy bits, in the form of a multiple number of the SDCLK period."<br>
Among others, this register should contain a 4bit timeout setting, "RTO[3:0]
Unknown which "multiple numbers" that's referring to (probably some exponential/table values).<br>
for SD (aka TO[3:0] for SDIO) timeout period for data start/busy bits, in the
form of a multiple number of the SDCLK period." Unknown which "multiple
numbers" that's referring to (probably some exponential/table values).
Settings spotted on DSi are 40E0h,40EEh.
Settings spotted on DSi are 40E0h,40EEh.
SD_RESPONSE0-7 = zerofilled
SD_RESPONSE0-7 = zerofilled
SD_IRQ_STATUS0-1 = all IRQs flags acknowledged
SD_IRQ_STATUS0-1 = all IRQs flags acknowledged
SD_ERROR_DETAIL_STATUS0-1 = all bits cleared (except bit13/always set)
SD_CARD_CLK_CTL = bit 8 and 10 cleared
SD_CARD_CLK_CTL = bit 8 and 10 cleared
SD_CARD_OPTION = 40EEh
SD_CARD_OPTION = 40EEh
3-0 Unknown (0)
3-0 Unknown (0)
===40048FAh - Can be 0004h..0007h (nonzero, unlike SDIO) (RESERVED6)===
===40048FAh - Can be 0007h (nonzero, unlike SDIO) (RESERVED6)===
15-3 Unknown (0)
15-3 Unknown (0)
2 Unknown (usually set) (R)
2 Unknown (1=normal, 0=data/read from card to fifo busy?) (R)
1-0 Unknown (0..3) (R/W? or rather R?)
1-0 Unknown (0..3) (R/W? or rather R?)