Registers

There's 4 NDMA channels. Arm7/Arm9 have separate NDMA.

NAME ADDRESS WIDTH
REG_NDMAGCNT 0x04004100 4
REG_NDMASAD(n) 0x04004104 + (n*0x1c) 4
REG_NDMADAD(n) 0x04004108 + (n*0x1c) 4
REG_NDMATCNT(n) 0x0400410c + (n*0x1c) 4
REG_NDMAWCNT(n) 0x04004110 + (n*0x1c) 4
REG_NDMABCNT(n) 0x04004114 + (n*0x1c) 4
REG_NDMAFDATA(n) 0x04004118 + (n*0x1c) 4
REG_NDMACNT(n) 0x0400411c + (n*0x1c) 4

REG_NDMAGCNT

BIT DESCRIPTION
19-16 Cycle selection.
31 DMA arbitration method. 0=Fixed method, 1=Round robin

REG_NDMASAD

BIT DESCRIPTION
31-0 Source data address. Must be multiple of 4.

Like old DMA, REG_NDMA_SRC is copied to internal registers when written to.

REG_NDMADAD

BIT DESCRIPTION
31-0 Destination data address. Must be multiple of 4.

Like old DMA, REG_NDMA_DEST is copied to internal registers when written to.

REG_NDMATCNT

BIT DESCRIPTION
31-0 Number of bytes to copy/write, see REG_NDMA_CNT bit28.

REG_NDMAWCNT

BIT DESCRIPTION
31-0 Number of bytes to copy/write, see REG_NDMA_CNT bit28.

REG_NDMABCNT

BIT DESCRIPTION
31-0 Time related?

REG_NDMAFDATA

BIT DESCRIPTION
31-0 Value to write to destination instead of copying when REG_NDMA_CNT bit13 and bit14 are set.

REG_NDMACNT

BIT DESCRIPTION
10-0 ?
11 Fixed destination address when set.
12 ?
13 When set clear data with the value REG_NDMA_CLEAR instead of copying.
14 Fixed source address when set.
27-15 ?
28 Set when REG_NDMA_NUM0 was set, clear when REG_NDMA_NUM1 was set.
30 IRQ enable
31 Enable/busy