Registers

There's 4 NDMA channels. Arm7/Arm9 have separate NDMA.

NAME ADDRESS WIDTH
REG_NDMA_MASTER_CNT 0x04004100 4
REG_NDMA_SRC(n) 0x04004104 + (n*0x1c) 4
REG_NDMA_DEST(n) 0x04004108 + (n*0x1c) 4
REG_NDMA_NUM0(n) 0x0400410c + (n*0x1c) 4
REG_NDMA_NUM1(n) 0x04004110 + (n*0x1c) 4
REG_NDMA_14(n) 0x04004114 + (n*0x1c) 4
REG_NDMA_CLEAR(n) 0x04004118 + (n*0x1c) 4
REG_NDMA_CNT(n) 0x0400411c + (n*0x1c) 4

REG_NDMA_MASTER_CNT

BIT DESCRIPTION
15-0 ?
16 Unknown, set when initialized by Arm7?
17 Unknown, set when initialized by Arm9?
18 Unknown, set when initialized by Arm7/Arm9?
30-19 ?
31 Might be master NDMA enable, when initialized this is set?

REG_NDMA_SRC

BIT DESCRIPTION
31-0 Source data address.

Like old DMA, REG_NDMA_SRC is copied to internal registers when written to.

REG_NDMA_DEST

BIT DESCRIPTION
31-0 Destination data address.

Like old DMA, REG_NDMA_DEST is copied to internal registers when written to.

REG_NDMA_NUM0

BIT DESCRIPTION
31-0 Number of bytes to copy/write, see REG_NDMA_CNT bit28.

REG_NDMA_NUM1

BIT DESCRIPTION
31-0 Number of bytes to copy/write, see REG_NDMA_CNT bit28.

REG_NDMA_14

BIT DESCRIPTION
31-0 Time related?

Once the CNT bit31 enable bit is set, starting doing the DMA once the time units specified by this register elapses?

REG_NDMA_CLEAR

BIT DESCRIPTION
31-0 Value to write to destination instead of copying when REG_NDMA_CNT bit13 and bit14 are set.

REG_NDMA_CNT

BIT DESCRIPTION
10-0 ?
11 Fixed destination address when set.
12 ?
13 When set clear data with the value REG_NDMA_CLEAR instead of copying.
14 Fixed source address when set.
27-15 ?
28 Set when REG_NDMA_NUM0 was set, clear when REG_NDMA_NUM1 was set.
30 IRQ enable
31 Enable/busy