Difference between revisions of "DSi cartridge header"

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Line 43: Line 43:
 
|  0x020
 
|  0x020
 
|  4
 
|  4
FLX ARM9 rom offset
+
|  ARM9 rom offset
 
|-
 
|-
 
|  0x024
 
|  0x024
 
|  4
 
|  4
FLX ARM9 entry address
+
|  ARM9 entry address
 
|-
 
|-
 
|  0x028
 
|  0x028
 
|  4
 
|  4
FLX ARM9 load address
+
|  ARM9 load address
 
|-
 
|-
 
|  0x02C
 
|  0x02C
 
|  4
 
|  4
FLX ARM9 size
+
|  ARM9 size
 
|-
 
|-
 
|  0x030
 
|  0x030
 
|  4
 
|  4
FLX ARM7 rom offset
+
|  ARM7 rom offset
 
|-
 
|-
 
|  0x034
 
|  0x034
 
|  4
 
|  4
FLX ARM7 entry address
+
|  ARM7 entry address
 
|-
 
|-
 
|  0x038
 
|  0x038
 
|  4
 
|  4
FLX ARM7 load address
+
|  ARM7 load address
 
|-
 
|-
 
|  0x03C
 
|  0x03C
 
|  4
 
|  4
FLX ARM7 size
+
|  ARM7 size
 
|-
 
|-
 
|  ...
 
|  ...
Line 87: Line 87:
 
|  0x1C0
 
|  0x1C0
 
|  4
 
|  4
LTD ARM9 rom offset
+
ARM9i rom offset
 
|-
 
|-
 
|  0x1C4
 
|  0x1C4
Line 95: Line 95:
 
|  0x1C8
 
|  0x1C8
 
|  4
 
|  4
LTD ARM9 load address
+
ARM9i load address
 
|-
 
|-
 
|  0x1CC
 
|  0x1CC
 
|  4
 
|  4
LTD ARM9 size
+
ARM9i size
 
|-
 
|-
 
|  0x1D0
 
|  0x1D0
 
|  4
 
|  4
LTD ARM7 rom offset
+
ARM7i rom offset
 
|-
 
|-
 
|  0x1D4
 
|  0x1D4
Line 111: Line 111:
 
|  0x1D8
 
|  0x1D8
 
|  4
 
|  4
LTD ARM7 load address
+
ARM7i load address
 
|-
 
|-
 
|  0x1DC
 
|  0x1DC
 
|  4
 
|  4
LTD ARM7 size
+
ARM7i size
 
|-
 
|-
 
|  ...
 
|  ...
Line 124: Line 124:
 
|  8
 
|  8
 
|  Title ID
 
|  Title ID
 +
|-
 +
|  ...
 +
|  ...
 +
|  ...
 +
|-
 +
|  0x300
 +
|  20
 +
|  ARM9 hash
 +
|-
 +
|  0x314
 +
|  20
 +
|  ARM7 hash
 +
|-
 +
|  0x328
 +
|  20
 +
|  ARM9i hash
 +
|-
 +
|  0x33C
 +
|  20
 +
|  ARM7i hash
 
|-
 
|-
 
|  ...
 
|  ...

Revision as of 02:11, 29 November 2009

OFFSET SIZE DESCRIPTION
0x000 12 Game Title
0x00C 4 Gamecode
0x010 2 Makercode
0x012 1 Unitcode
0x013 1 Encryption seed select
0x014 1 Devicecapacity
0x015 9 Reserved
0x01E 1 ROM Version
0x01F 1 Autostart
0x020 4 ARM9 rom offset
0x024 4 ARM9 entry address
0x028 4 ARM9 load address
0x02C 4 ARM9 size
0x030 4 ARM7 rom offset
0x034 4 ARM7 entry address
0x038 4 ARM7 load address
0x03C 4 ARM7 size
... ... Fill me in
0x1B8 4 ARM7 SCFG EXT mask (controls which devices to enable)
0x1BC 4 ...
0x1C0 4 ARM9i rom offset
0x1C4 4 ?
0x1C8 4 ARM9i load address
0x1CC 4 ARM9i size
0x1D0 4 ARM7i rom offset
0x1D4 4 ?
0x1D8 4 ARM7i load address
0x1DC 4 ARM7i size
... ... ...
0x230 8 Title ID
... ... ...
0x300 20 ARM9 hash
0x314 20 ARM7 hash
0x328 20 ARM9i hash
0x33C 20 ARM7i hash
... ... ...
0xE00 0x180 Reserved and unchecked region, always zero
0xF80 0x80 RSA signature

The first 0xE00 bytes of the SRL header is signed with an 1024-bit RSA signature.