108
edits
Changes
SD/MMC/SDIO Registers (view source)
Revision as of 11:44, 2 September 2015
, 11:44, 2 September 2015→400482Ch/4004A2Ch - SD_ERROR_DETAIL_STATUS0-1 - Error Detail Status
===400482Ch/4004A2Ch - SD_ERROR_DETAIL_STATUS0-1 - Error Detail Status===
===400482Ch/4004A2Ch - SD_ERROR_DETAIL_STATUS0-1 - Error Detail Status===
31-23 ? Unknown/unused/undoc
This register contains extra info about the error bits in SD_IRQ_STATUS. The error bits (except bit13/always set) are automatically cleared when sending a new command by writing to SD_CMD.
22 KBSY Timeout for CRC status busy timeout ;\STAT.19
31-23 0 Unknown/unused (always zero)
21 NWCS Timeout for CRC status timeout ; (SDTO)
22 KBSY Timeout for CRC status busy ;\STAT.19
21 NWCS Timeout for CRC status (can occur for Data Write) ; (SDTO)
20 NRCS Timeout for Data start-bit, or for Post Data Busy ;/
20 NRCS Timeout for Data start-bit, or for Post Data Busy ;/
19-18 ? Unknown/unused/undoc
19-18 0 Unknown/unused (always zero)
17 NRS Response timeout for auto-issued CMD12 ;\STAT.22
17 NRS Response Timeout for auto-issued CMD12 ;\STAT.22
16 NCR Response timeout for non-auto-issued CMD's ;/(SCTO)
16 NCR Response Timeout for non-auto-issued CMD's ;/(SCTO)
15-14 ? Unknown/unused/undoc
15-14 0 Unknown/unused (always zero)
13 ?? Unknown/undoc (bit13 can be nonzero on DSi!) (always 1?) (R?)
13 undoc Unknown/undoc (always 1) ;-Always 1
12 ? Unknown/unused/undoc
12 0 Unknown/unused (always zero)
11 WCRCE CRC error for Write CRC status for a write command ;\
11 WCRCE CRC error for Write CRC status for a write command ;\
10 RCRCE CRC error for read data ; STAT.17
10 RCRCE CRC error for Read Data ; STAT.17
9 SCRCE CRC error for a response for auto-issued CMD12 ; (SCRC)
9 SCRCE CRC error for a Response for auto-issued CMD12 ; (SCRC)
8 CCRCE CRC error for a response for non-auto-issued CMD's ;/
8 CCRCE CRC error for a Response for non-auto-issued CMD's ;/
5 WEBER End bit error for Write CRC status ;\
5 WEBER End bit error for Write CRC status ;\
4 REBER End bit error for read data ; STAT.18
4 REBER End bit error for Read Data ; STAT.18
3 SEBER End bit error for response for auto-issued CMD12 ; (SEND)
3 SEBER End bit error for Response for auto-issued CMD12 ; (SEND)
2 CEBER End bit error for response for non-auto-issued CMD's ;/
2 CEBER End bit error for Response for non-auto-issued CMD's ;/
1? SCMDE Bad CMD-index in response of auto-issued CMD12 ;\STAT.16
1? SCMDE Bad CMD-index in Response of auto-issued CMD12 ;\STAT.16
0 RCMDE Bad CMD-index in response of non-auto-issued CMD's ;/(SCIX)
0 RCMDE Bad CMD-index in Response of non-auto-issued CMD's ;/(SCIX)
Note: CMD12 is STOP_TRANSMISSION (automatically sent after BLK_COUNT blocks).<br>
Note: CMD12 is STOP_TRANSMISSION (maybe sent after BLK_COUNT?).<br>
The four "auto-issued CMD12" bits exist for SD registers only (not for SDIO, going by old toshiba datasheets; which may be wrong).
The four "auto-issued CMD12" bits exist for SD registers only (not SDIO).<br>
SCMDE is probably in bit1 (though, official specs say bit0, which would be same as RCMDE).<br>
SCMDE is probably in bit1 (though, official specs say bit0, which would be same as RCMDE).
Some error bits can be intentionally provoked: Bit8=1 when programming the controller to expect GET_STATUS to return a 136bit response. Bit16=1 when sending GET_CID in "tran" state. Bit20=1 when sending GET_STATUS configured to expect a data/read reply. Bit21=1 when sending GET_STATUS configured to expect a data/write block (and with actually sending a data block to it).
== DSi SD/MMC I/O Ports: Control Registers ==
== DSi SD/MMC I/O Ports: Control Registers ==