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Acknowledge by writing CINT0=0, or CIMSK0=1, or hard reset (unlike as for other
Acknowledge by writing CINT0=0, or CIMSK0=1, or hard reset (unlike as for other
SD/MMC interrupts, soft reset does not acknowlege this interrupt type?).
SD/MMC interrupts, soft reset does not acknowlege this interrupt type?).
== DSi SD/MMC I/O Ports: Control ==
'''4004802h - SD_CARD_PORT_SELECT (0201h)'''<br>
'''4004A02h - SDIO_CARD_PORT_SELECT (0100h)'''<br>
15-11 Unknown/unused (appears to be always zero)
10 Unknown (write: should be 1, read: usually/always 0) (W?)
9 Unknown (write: should be 0, read: usually 1 for SD)
8 Unknown (write: should be 0, read: usually 1 for SDIO)
7-4 Unknown/unused (appears to be always zero)
3-1 Unknown (R/W)
0 Port Select (0=SD Card Slot, 1=Onboard eMMC) (for SDIO: Unknown)
Known written values are 0400h and 0401h (SD). However known read values are
0201h (SD) and 0100h (SDIO).
'''4004828h - DSi: 40E0 - SD_CARD_OPTION - Memory Card Option Setup'''<br>
'''4004A28h - DSi: 40EE - SDIO_CARD_OPTION - Card Option Setup'''<br>
15 Bus Width (0=4bit, 1=1bit)
14 Unknown (usually set)
13-8 Unknown/unused (appears to be always zero)
7-4 Unknown, maybe some 4bit timing/timeout value
0-3 Unknown, maybe another 4bit timing/timeout value
Settings spotted on DSi are 40E0h,40EEh.<br>
Among others, this register should contain a 4bit timeout setting, "RTO[3:0]
for SD (aka TO[3:0] for SDIO) timeout period for data start/busy bits, in the
form of a multiple number of the SDCLK period."<br>
Maybe also selects transfer CLK rate, or whatever.
'''4004834h - DSi: 0000 - SD_TRANSACTION_CTL - Transaction Control'''<br>
'''4004A34h - DSi: 0000 - SDIO_TRANSACTION_CTL - Transaction Control'''<br>
15-10 Unknown/unused (appears to be always zero)
9-8 Unknown
7-3 Unknown/unused (appears to be always zero)
2 Unknown
1 Unknown/unused (appears to be always zero)
0 Unknown
Maybe also selects transfer CLK rate, or whatever.
'''40048E0h - DSi: 0007 - SD_SOFT_RESET - Software Reset'''<br>
'''4004AE0h - DSi: 0006 - SDIO_SOFT_RESET - Software Reset'''<br>
15-3 Unknown/unused (appears to be always zero)
2 ? Unknown (can be nonzero on DSi)
1 ? Unknown (can be nonzero on DSi)
0 SRST Soft Reset (0=Reset, 1=Release)
Software should apply reset after sensing card insertion/removal, and
(thereafter) release reset in case of card insertion. Software reset does
acknowledge all IRQs (except that from SDIO /IRQ pin?), and does probably also
reinitialize some other registers.
'''4004808h - DSi: 0100 - SDCTL_STOP_INTERNAL_ACTION'''<br>
15-9 Unknown/unused (appears to be always zero)
8 Unknown
7-1 Unknown/unused (appears to be always zero)
0 Unknown
Stop whatever internal action for whatever purpose in whatever situation?<br>
Existing code does set bit8 (prior to changing SD_DATA16_BLK_COUNT).<br>
Existing code does clear bit0 (alongsides with IRQ enable/acknowlege or so).
'''4004824h - DSi: 0000 - DSi: Used? - SDCTL_CARD_CLK_CTL Card Clock Control'''<br>
Can be max 07FFh on DSi... ie. bit15 CANNOT be set?
15 Disable HCLK divider (0=SDCLK selected via bit7-0, 1=SDCLK=HCLK)
14-10 Unknown (zero on DSi)
9 Unknown (set in some cases on DSi)
8 Unknown (1=Start Clock, or Apply Clock Change, or so?)
7-0 HCLK Div (0,1,2,4,8,10h,20h,40h,80h = Div2,4,8,16,32,64,128,256,512)
Clock supply to SD Card<br>
The SDCLK signal is used for a provision of SD Memory Card or SDIO Card. Please
refer to the following setting for enabling the SDCLK output.
(1) Set Stop Clock Control Register (Config Offset:40h) to 1Fh.
(2) Set D0 of SD Software Reset Register (Offset:0E0h) to 1b.
(3) Set D7-0 of SD Card Clock Control Register (Offset:024h). These bits
are used for setting the frequency of SDCLK.
80h : SDCLK=HCLK/512
40h : SDCLK=HCLK/256
20h : SDCLK=HCLK/128
10h : SDCLK=HCLK/64
08h : SDCLK=HCLK/32
04h : SDCLK=HCLK/16
02h : SDCLK=HCLK/8
01h : SDCLK=HCLK/4
00h : SDCLK=HCLK/2
In addition, TC6387XB holds a function that SDCLK can have same
frequency as HCLK. In this case, D7-0 settings of SD Card Clock Control
Register (Offset:024h) becomes invalid setting.
* Set D0 of Clock Mode Register (Config Offset:42h) to 1b.
* Set D15 of SD Card Clock Control Register (Offset:024h) to 1b.
Please attend that the specification of SDCLK is max.25MHz at the case
of SD Card and is max.20MHz at the case of MultiMedia Card.
(4) D8 of SD Card Clock Control Register (Offset:024h) to 1b.
(5) D8 of Clock & Wait Control Register (Offset:138h) to 1b.
On the DSi, HCLK seems to be 33.513982 MHz.
'''4004x38h - DSi: 0000 - SDCTL_CLK_AND_WAIT_CTL'''<br>
15-0 Unknown (zero on DSi)
Maybe transfer CLK rate, or some master clock control for the clock input.
'''4004x3Ah - DSi: 0000 - SDCTL_SDIO_HOST_INFORMATION'''<br>
'''4004x3Ch - DSi: 0000 - SDCTL_ERROR_CONTROL'''<br>
'''4004x3Eh - DSi: 0000 - SDCTL_SDLED_CONTROL - LED Control (TC6387XB only)'''<br>
15-0 Unknown (zero on DSi)
'''40048E2h - DSi: 0009 - SDCTL_RESERVED2 (TC6371AF:CORE_REV)'''<br>
'''40048E6h - DSi: 0000 - SDCTL_RESERVED3 (TC6371AF:BUF_ADR)'''<br>
'''40048E8h - DSi: 0000 - UNDOC/UNUSED (TC6371AF:Resp_Header)'''<br>
'''40048F6h - DSi: 0000 - SDCTL_RESERVED4 --- used by DSi !!!'''<br>
'''40048F8h - DSi: 0004 - SDCTL_RESERVED5 <-- DSi: SD only (not SDIO)'''<br>
'''40048FAh - DSi: 0007 - SDCTL_RESERVED6 <-- DSi: SD only (not SDIO)'''<br>
'''40048FCh - DSi: 00FC - SDCTL_RESERVED7'''<br>
'''40048FEh - DSi: 00FF - SDCTL_RESERVED8 (TC6371AF:Revision)'''<br>
'''4004xE2h - DSi: 0000 - SDCTL_RESERVED9'''<br>
'''4004xF0h - DSi: 0000 - SDCTL_RESERVED10'''<br>
'''4004836h - DSi: 0002 - UNDOC! (bit1 can be set, other bits always 0)'''<br>
15-0 Unknown
'''4004838h/4004A38h - DSi: C007 - UNDOC!'''<br>
'''4004840h/4004A40h - DSi: 003F - UNDOC?'''<br>
'''4004842h/4004A42h - DSi: 002A - UNDOC?'''<br>
'''40048B2h/4004AB2h - DSi: FFFF - UNDOC?'''<br>
'''40048BAh/4004ABAh - DSi: 0200 - UNDOC?'''<br>
'''40048F4h/4004AF4h - DSi: 0700 - UNDOC!'''<br>
15-0 Unknown