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Created page with "== DSi SD/MMC I/O Ports: Command/Param/Response/Data == '''4004800h - SD_CMD - Command and Response/Data Type (R/W)'''<br> '''4004A00h - SDIO_CMD - Command and Response/Data Typ..."
== DSi SD/MMC I/O Ports: Command/Param/Response/Data ==
'''4004800h - SD_CMD - Command and Response/Data Type (R/W)'''<br>
'''4004A00h - SDIO_CMD - Command and Response/Data Type (R/W)'''<br>
15 undoc Unknown/undoc (read/write-able)
14 undoc Security Cmd (0=Normal, 1=Whatever/Security) (sdio?)
13 undoc Data Length (0=Single Block, 1=Multiple Blocks)
12 undoc Data Direction (0=Write, 1=Read)
11 NTDT Data Transfer (0=No data, 1=With data)
10-8 REP2-0 Response Type (0..2=Unknown/Reserved, 3=None, 4=48bit,
5=48bit+Busy, 6=136bit, 7=48bitOcrWithoutCRC7)
7-6 CMD1-0 Command Type (0=CMD, 1=ACMD, 2..3=unknown, maybe GEN WR/RD?)
5-0 CIX Command Index (0..3Fh, command index)
Invalid values can cause ILA error (particulary on setting NTDT for CMD12, or
for CMD's Response=None). ILA error will also occur if an old CMD is still
busy.
DSi software is always writing just ZERO to bit11-6 though? Maybe the hardware
does automatically know which SD/MMC CMDs and ACMDs have data? Or maybe data is
always automatically transferred when receiving a data-startbit, or when
writing to data register - and bits like NTDT would be needed only for things
like proper data timeout handling?
'''4004804h - SD_CMD_PARAM0-1 - Argument (32bit, 2 halfwords) (R/W)'''<br>
'''4004A04h - SDIO_CMD_PARAM0-1 - Argument (32bit, 2 halfwords) (R/W)'''<br>
31-0 Parameter value for CMD
The parameter value should be written <before> sending the command via
SD_CMD/SDIO_CMD.
'''400480Ch - SD_RESPONSE0-7 - Response (128bit, 8 halfwords) (R)'''<br>
'''4004A0Ch - SDIO_RESPONSE0-7 - Response (128bit, 8 halfwords) (R)'''<br>
After sending a command, wait for the CMDRESPEND bit (IRQ_STATUS.bit0) to get
set, then read the RESPONSE (if the command does have any response).
For normal 32bit responses:
31-0 Response
127-32 Older Responses
For CID/CSD responses:
119-0 120bit Response
127-120 Zero (always?)
Seems to be left-shifted when receiving response bits. So, for 32bit responses,
bit0-31 would contain the current response, and bit32-127 would contain older
responses.
'''DATA16 vs DATA32'''<br>
Data can be transferred in 16bit or 32bit units (as selected in DATA_CTL.bit1).
There are separate data, block len, and block count registers for 16bit and
32bit mode (that's probably due to some odd patchwork, where the manufacturer
has added 32bit support to the original 16bit chip design).
Naturally, a 32bit transfer is faster than two 16bit transfers. Nethertheless,
the DSi firmware does use both 32bit and 16bit mode once and then; 32bit mode
is required for NDMA transfers (which don't support 16bit).
'''40048D8h - SD_DATA_CTL'''<br>
'''4004AD8h - SDIO_DATA_CTL'''<br>
15-13 Unknown (usually 0)
12 Unknown (usually 1) (R?)
11-6 Unknown (usually 0)
5 Unknown (R/W?) (R/W?)
4 Unknown (usually 1) (R?)
3-2 Unknown (usually 0)
1 Select 16bit/32bit Data Mode (0=DATA16, 1=DATA32) (R/W?)
0 Unknown (usually 0)
Known written values are 0000h and 0002h. However, known read values are 1010h
and 1012h.
'''400480Ah - SD_DATA16_BLK_COUNT - "Transfer Sector Count" (R/W)'''<br>
'''4004908h - SD_DATA32_BLK_COUNT (R/W)'''<br>
'''4004A0Ah - SDIO_DATA16_BLK_COUNT - "Transfer Block Count" (R/W)'''<br>
'''4004B08h - SDIO_DATA32_BLK_COUNT (R/W)'''<br>
15-0 Number of Data Blocks for multiple read/write commands
Can be max FFFFh. The DATA32_BLK_COUNT value decreases after reading from
somewhere (maybe from DATA32_FIFO?).
'''4004826h - SD_DATA16_BLK_LEN - Memory Card Transfer Data Length (R/W)'''<br>
'''4004904h - SD_DATA32_BLK_LEN (R/W)'''<br>
'''4004A26h - SDIO_DATA16_BLK_LEN - Card Transfer Data Length (R/W)'''<br>
'''4004B04h - SDIO_DATA32_BLK_LEN (R/W)'''<br>
15-10 Unknown/unused (appears to be always zero)
9-0 Data Block Length in bytes (for DATA16: clipped to max 0200h by hw)
Should be usually 0200h (for 512-byte SD/MMC memory blocks). Other values may
be needed for SDIO functions, or when accessing SSR/SCR/PWD registers via data
transfers.
DATA32_BLK_LEN can be max 3FFh (unlike DATA16_BLK_LEN which is clipped to
max=200h by hardware).
'''4004830h - SD_DATA16_FIFO - Data Port (SD_FIFO?)'''<br>
'''400490Ch - SD_DATA32_FIFO'''<br>
'''4004A30h - SDIO_DATA16_FIFO - Data Port (SD_FIFO?)'''<br>
'''4004B0Ch - SDIO_DATA32_FIFO'''<br>
For Data16:
15-0 Data (16bit) (...or could it be accessed as 32bit, too?)
For Data32:
31-0 Data (32bit) (...or could it be accessed as 16bit, too?)
Transfer data here (read after RXRDY gets set, or write after TXRQ gets set).
FIFO size is unknown (if there's any FIFO behind it).
== DSi SD/MMC I/O Ports: Interrupt/Status ==
'''400481Ch - SD_IRQ_STATUS0-1 - Interrupt Status (R/ack)'''<br>
'''4004A1Ch - SDIO_IRQ_STATUS0-1 - Interrupt Status (R/ack)'''<br>
'''4004820h - SD_IRQ_MASK0-1 - Interrupt Mask (R/W)'''<br>
'''4004A20h - SDIO_IRQ_MASK0-1 - Interrupt Mask (R/W)'''<br>
IRQ Status (0=ack, 1=request)<br>
IRQ Mask (0=Enable, 1=Disable)<br>
Bit Stat Mask Function
0 SREP MREP CMDRESPEND (response end) (or R1b: busy end)
1 ? - Unknown/unused/undoc
2 SRWA MRWA DATAEND (is NOT set? after data read/write end bit)
3 SCOT MCOT CARD_REMOVE ;\SD only (not SDIO)
4 SCIN MCIN CARD_INSERT ;/
5 undoc - SIGSTATE card/type/signal/signature detect?
6 ? - Unknown/unused/undoc maybe card-detect switch?
7 undoc - WRPROTECT probably write-protect switch
8 undoc undoc CARD_REMOVE_A ;\
9 undoc undoc CARD_INSERT_A ; uh, somewhat dupes of bit3-5?
10 undoc - SIGSTATE_A ;/
11 ? - Unknown/unused/undoc
12 ? - Unknown/unused/undoc
13 ? - Unknown/unused/undoc
14 ? - Unknown/unused/undoc
15 ? - Unknown/unused/undoc
16 SCIX MCIX CMD_IDX_ERR Bad CMD-index in response (RCMDE,SCMDE)
17 SCRC MCRC CRCFAIL CRC response error (WCRCE,RCRCE,SCRCE,CCRCE)
18 SEND MEND STOPBIT_ERR End bit error (WEBER,REBER,SEBER,CEBER)
19 SDTO MDTO DATATIMEOUT Data Timeout (NRCS,NWCS,KBSY)
20 SFOF MFOF RXOVERFLOW HOST tried write full
21 SFUF MFUF TXUNDERRUN HOST tried read empty
22 SCTO MCTO CMDTIMEOUT Response start-bit timeout (NRS,NSR)
23 ? - Unknown/unused/undoc
24 SBRE MBRE RXRDY (fifo not empty) (request data read)
25 SBWE MBWE TXRQ (datafifoempty?) (request data write)
26 ? - Unknown/unused/undoc
27 undoc undoc Unknown/used?! (the bit is mask-able in IRQ_MASK)
28 ? - Unknown/unused/undoc
29 undoc - DSi: Unknown/can be 1 (not exactly like below Toshiba specs)
(29) ILFSL IFSMSK Toshiba: ILL_FUNC Illegal SDIO Function ;SDIO only (not SD)
30 undoc - CMD_BUSY
31 ILA IMSK Illegal Command Access (old CMD still busy, or wrong NTDT)
Acknowledge by STAT=0, or by MASK=1 (uh, really?), or by soft reset (SRST=0) or
hard reset.<br>
The Insert/Remove bits (bit3,4, and maybe also bit8,9) exist in the "SD"
registers only, not in the "SDIO" registers (the bits should be treated as
general insert/remove flags though, no matter if the card is an SD or SDIO
card).<br>
Bit29 is SDIO related, and exist in SDIO registers only, not in SD registers.
4004820h can be 8B7F031Dh
4004A20h can be 8B7F031Dh
'''4004900h - SD_DATA32_IRQ'''<br>
'''4004B00h - SDIO_DATA32_IRQ'''<br>
15-13 Unknown/unused (appears to be always zero)
12 Unknown (paired with bit9) (can be set) IRQ enable ?! (R/W?)
11 Unknown (paired with bit8) (can be set) IRQ enable ?! (R/W?)
10 Unknown (read=0) write: (0=No change, 1=Clear Bit8,9) ? (W?)
9 Unknown (paired with bit12) (automatically cleared after...) (R?)
8 Unknown (paired with bit11) (R?)
7-2 Unknown (0)
1 Unknown (can be set) (autoclear bit8,9 on xfer end?) (R/W?)
0 Unknown (0)
Can be 1A02h, but changes to 1802h after reading from somewhere (maybe from
DATA32_FIFO?).<br>
Bit8,9 seem to be whatever extra IRQ flags, the flags get set ONLY in DATA32
mode (not in DATA16 mode).
'''400482Ch - SD_ERROR_DETAIL_STATUS0-1 - Error Detail Status'''<br>
'''4004A2Ch - SDIO_ERROR_DETAIL_STATUS0-1 - Error Detail Status'''<br>
31-23 ? Unknown/unused/undoc
22 KBSY Timeout for CRC status busy timeout ;\STAT.19
21 NWCS Timeout for CRC status timeout ; (SDTO)
20 NRCS Timeout for Data start-bit, or for Post Data Busy ;/
19-18 ? Unknown/unused/undoc
17 NRS Response timeout for auto-issued CMD12 ;\STAT.22
16 NCR Response timeout for non-auto-issued CMD's ;/(SCTO)
15-14 ? Unknown/unused/undoc
13 ?? Unknown/undoc (bit13 can be nonzero on DSi!)
12 ? Unknown/unused/undoc
11 WCRCE CRC error for Write CRC status for a write command ;\
10 RCRCE CRC error for read data ; STAT.17
9 SCRCE CRC error for a response for auto-issued CMD12 ; (SCRC)
8 CCRCE CRC error for a response for non-auto-issued CMD's ;/
5 WEBER End bit error for Write CRC status ;\
4 REBER End bit error for read data ; STAT.18
3 SEBER End bit error for response for auto-issued CMD12 ; (SEND)
2 CEBER End bit error for response for non-auto-issued CMD's ;/
1? SCMDE Bad CMD-index in response of auto-issued CMD12 ;\STAT.16
0 RCMDE Bad CMD-index in response of non-auto-issued CMD's ;/(SCIX)
Unknown if/when/how the error bits can be reset/acknowledged.<br>
Note: CMD12 is STOP_TRANSMISSION (maybe sent after BLK_COUNT?).<br>
The four "auto-issued CMD12" bits exist for SD registers only (not SDIO).
SCMDE is probably in bit1 (though, official specs say bit0, which would be same
as RCMDE).
'''4004A36h - DSi: 0000 - SDCTL_CARD_INTERRUPT_CONTROL'''<br>
This does NOT seem to be implemented as described below on DSi.
4004A36h does seem to behave more like 4004836h, see there.
15-13 ? Unknown (zero on DSi)
12 CINT0 SDIO Interrupt Flag (0=none, 1=irq) (/IRQ aka Data1 pin)
11-9 ? Unknown (zero on DSi)
8 CIMSK0 SDIO Interrupt Mask (0=enable, 1=disable) (/IRQ aka Data1 pin)
7-0 ? Unknown (zero on DSi)
Acknowledge by writing CINT0=0, or CIMSK0=1, or hard reset (unlike as for other
SD/MMC interrupts, soft reset does not acknowlege this interrupt type?).
'''4004800h - SD_CMD - Command and Response/Data Type (R/W)'''<br>
'''4004A00h - SDIO_CMD - Command and Response/Data Type (R/W)'''<br>
15 undoc Unknown/undoc (read/write-able)
14 undoc Security Cmd (0=Normal, 1=Whatever/Security) (sdio?)
13 undoc Data Length (0=Single Block, 1=Multiple Blocks)
12 undoc Data Direction (0=Write, 1=Read)
11 NTDT Data Transfer (0=No data, 1=With data)
10-8 REP2-0 Response Type (0..2=Unknown/Reserved, 3=None, 4=48bit,
5=48bit+Busy, 6=136bit, 7=48bitOcrWithoutCRC7)
7-6 CMD1-0 Command Type (0=CMD, 1=ACMD, 2..3=unknown, maybe GEN WR/RD?)
5-0 CIX Command Index (0..3Fh, command index)
Invalid values can cause ILA error (particulary on setting NTDT for CMD12, or
for CMD's Response=None). ILA error will also occur if an old CMD is still
busy.
DSi software is always writing just ZERO to bit11-6 though? Maybe the hardware
does automatically know which SD/MMC CMDs and ACMDs have data? Or maybe data is
always automatically transferred when receiving a data-startbit, or when
writing to data register - and bits like NTDT would be needed only for things
like proper data timeout handling?
'''4004804h - SD_CMD_PARAM0-1 - Argument (32bit, 2 halfwords) (R/W)'''<br>
'''4004A04h - SDIO_CMD_PARAM0-1 - Argument (32bit, 2 halfwords) (R/W)'''<br>
31-0 Parameter value for CMD
The parameter value should be written <before> sending the command via
SD_CMD/SDIO_CMD.
'''400480Ch - SD_RESPONSE0-7 - Response (128bit, 8 halfwords) (R)'''<br>
'''4004A0Ch - SDIO_RESPONSE0-7 - Response (128bit, 8 halfwords) (R)'''<br>
After sending a command, wait for the CMDRESPEND bit (IRQ_STATUS.bit0) to get
set, then read the RESPONSE (if the command does have any response).
For normal 32bit responses:
31-0 Response
127-32 Older Responses
For CID/CSD responses:
119-0 120bit Response
127-120 Zero (always?)
Seems to be left-shifted when receiving response bits. So, for 32bit responses,
bit0-31 would contain the current response, and bit32-127 would contain older
responses.
'''DATA16 vs DATA32'''<br>
Data can be transferred in 16bit or 32bit units (as selected in DATA_CTL.bit1).
There are separate data, block len, and block count registers for 16bit and
32bit mode (that's probably due to some odd patchwork, where the manufacturer
has added 32bit support to the original 16bit chip design).
Naturally, a 32bit transfer is faster than two 16bit transfers. Nethertheless,
the DSi firmware does use both 32bit and 16bit mode once and then; 32bit mode
is required for NDMA transfers (which don't support 16bit).
'''40048D8h - SD_DATA_CTL'''<br>
'''4004AD8h - SDIO_DATA_CTL'''<br>
15-13 Unknown (usually 0)
12 Unknown (usually 1) (R?)
11-6 Unknown (usually 0)
5 Unknown (R/W?) (R/W?)
4 Unknown (usually 1) (R?)
3-2 Unknown (usually 0)
1 Select 16bit/32bit Data Mode (0=DATA16, 1=DATA32) (R/W?)
0 Unknown (usually 0)
Known written values are 0000h and 0002h. However, known read values are 1010h
and 1012h.
'''400480Ah - SD_DATA16_BLK_COUNT - "Transfer Sector Count" (R/W)'''<br>
'''4004908h - SD_DATA32_BLK_COUNT (R/W)'''<br>
'''4004A0Ah - SDIO_DATA16_BLK_COUNT - "Transfer Block Count" (R/W)'''<br>
'''4004B08h - SDIO_DATA32_BLK_COUNT (R/W)'''<br>
15-0 Number of Data Blocks for multiple read/write commands
Can be max FFFFh. The DATA32_BLK_COUNT value decreases after reading from
somewhere (maybe from DATA32_FIFO?).
'''4004826h - SD_DATA16_BLK_LEN - Memory Card Transfer Data Length (R/W)'''<br>
'''4004904h - SD_DATA32_BLK_LEN (R/W)'''<br>
'''4004A26h - SDIO_DATA16_BLK_LEN - Card Transfer Data Length (R/W)'''<br>
'''4004B04h - SDIO_DATA32_BLK_LEN (R/W)'''<br>
15-10 Unknown/unused (appears to be always zero)
9-0 Data Block Length in bytes (for DATA16: clipped to max 0200h by hw)
Should be usually 0200h (for 512-byte SD/MMC memory blocks). Other values may
be needed for SDIO functions, or when accessing SSR/SCR/PWD registers via data
transfers.
DATA32_BLK_LEN can be max 3FFh (unlike DATA16_BLK_LEN which is clipped to
max=200h by hardware).
'''4004830h - SD_DATA16_FIFO - Data Port (SD_FIFO?)'''<br>
'''400490Ch - SD_DATA32_FIFO'''<br>
'''4004A30h - SDIO_DATA16_FIFO - Data Port (SD_FIFO?)'''<br>
'''4004B0Ch - SDIO_DATA32_FIFO'''<br>
For Data16:
15-0 Data (16bit) (...or could it be accessed as 32bit, too?)
For Data32:
31-0 Data (32bit) (...or could it be accessed as 16bit, too?)
Transfer data here (read after RXRDY gets set, or write after TXRQ gets set).
FIFO size is unknown (if there's any FIFO behind it).
== DSi SD/MMC I/O Ports: Interrupt/Status ==
'''400481Ch - SD_IRQ_STATUS0-1 - Interrupt Status (R/ack)'''<br>
'''4004A1Ch - SDIO_IRQ_STATUS0-1 - Interrupt Status (R/ack)'''<br>
'''4004820h - SD_IRQ_MASK0-1 - Interrupt Mask (R/W)'''<br>
'''4004A20h - SDIO_IRQ_MASK0-1 - Interrupt Mask (R/W)'''<br>
IRQ Status (0=ack, 1=request)<br>
IRQ Mask (0=Enable, 1=Disable)<br>
Bit Stat Mask Function
0 SREP MREP CMDRESPEND (response end) (or R1b: busy end)
1 ? - Unknown/unused/undoc
2 SRWA MRWA DATAEND (is NOT set? after data read/write end bit)
3 SCOT MCOT CARD_REMOVE ;\SD only (not SDIO)
4 SCIN MCIN CARD_INSERT ;/
5 undoc - SIGSTATE card/type/signal/signature detect?
6 ? - Unknown/unused/undoc maybe card-detect switch?
7 undoc - WRPROTECT probably write-protect switch
8 undoc undoc CARD_REMOVE_A ;\
9 undoc undoc CARD_INSERT_A ; uh, somewhat dupes of bit3-5?
10 undoc - SIGSTATE_A ;/
11 ? - Unknown/unused/undoc
12 ? - Unknown/unused/undoc
13 ? - Unknown/unused/undoc
14 ? - Unknown/unused/undoc
15 ? - Unknown/unused/undoc
16 SCIX MCIX CMD_IDX_ERR Bad CMD-index in response (RCMDE,SCMDE)
17 SCRC MCRC CRCFAIL CRC response error (WCRCE,RCRCE,SCRCE,CCRCE)
18 SEND MEND STOPBIT_ERR End bit error (WEBER,REBER,SEBER,CEBER)
19 SDTO MDTO DATATIMEOUT Data Timeout (NRCS,NWCS,KBSY)
20 SFOF MFOF RXOVERFLOW HOST tried write full
21 SFUF MFUF TXUNDERRUN HOST tried read empty
22 SCTO MCTO CMDTIMEOUT Response start-bit timeout (NRS,NSR)
23 ? - Unknown/unused/undoc
24 SBRE MBRE RXRDY (fifo not empty) (request data read)
25 SBWE MBWE TXRQ (datafifoempty?) (request data write)
26 ? - Unknown/unused/undoc
27 undoc undoc Unknown/used?! (the bit is mask-able in IRQ_MASK)
28 ? - Unknown/unused/undoc
29 undoc - DSi: Unknown/can be 1 (not exactly like below Toshiba specs)
(29) ILFSL IFSMSK Toshiba: ILL_FUNC Illegal SDIO Function ;SDIO only (not SD)
30 undoc - CMD_BUSY
31 ILA IMSK Illegal Command Access (old CMD still busy, or wrong NTDT)
Acknowledge by STAT=0, or by MASK=1 (uh, really?), or by soft reset (SRST=0) or
hard reset.<br>
The Insert/Remove bits (bit3,4, and maybe also bit8,9) exist in the "SD"
registers only, not in the "SDIO" registers (the bits should be treated as
general insert/remove flags though, no matter if the card is an SD or SDIO
card).<br>
Bit29 is SDIO related, and exist in SDIO registers only, not in SD registers.
4004820h can be 8B7F031Dh
4004A20h can be 8B7F031Dh
'''4004900h - SD_DATA32_IRQ'''<br>
'''4004B00h - SDIO_DATA32_IRQ'''<br>
15-13 Unknown/unused (appears to be always zero)
12 Unknown (paired with bit9) (can be set) IRQ enable ?! (R/W?)
11 Unknown (paired with bit8) (can be set) IRQ enable ?! (R/W?)
10 Unknown (read=0) write: (0=No change, 1=Clear Bit8,9) ? (W?)
9 Unknown (paired with bit12) (automatically cleared after...) (R?)
8 Unknown (paired with bit11) (R?)
7-2 Unknown (0)
1 Unknown (can be set) (autoclear bit8,9 on xfer end?) (R/W?)
0 Unknown (0)
Can be 1A02h, but changes to 1802h after reading from somewhere (maybe from
DATA32_FIFO?).<br>
Bit8,9 seem to be whatever extra IRQ flags, the flags get set ONLY in DATA32
mode (not in DATA16 mode).
'''400482Ch - SD_ERROR_DETAIL_STATUS0-1 - Error Detail Status'''<br>
'''4004A2Ch - SDIO_ERROR_DETAIL_STATUS0-1 - Error Detail Status'''<br>
31-23 ? Unknown/unused/undoc
22 KBSY Timeout for CRC status busy timeout ;\STAT.19
21 NWCS Timeout for CRC status timeout ; (SDTO)
20 NRCS Timeout for Data start-bit, or for Post Data Busy ;/
19-18 ? Unknown/unused/undoc
17 NRS Response timeout for auto-issued CMD12 ;\STAT.22
16 NCR Response timeout for non-auto-issued CMD's ;/(SCTO)
15-14 ? Unknown/unused/undoc
13 ?? Unknown/undoc (bit13 can be nonzero on DSi!)
12 ? Unknown/unused/undoc
11 WCRCE CRC error for Write CRC status for a write command ;\
10 RCRCE CRC error for read data ; STAT.17
9 SCRCE CRC error for a response for auto-issued CMD12 ; (SCRC)
8 CCRCE CRC error for a response for non-auto-issued CMD's ;/
5 WEBER End bit error for Write CRC status ;\
4 REBER End bit error for read data ; STAT.18
3 SEBER End bit error for response for auto-issued CMD12 ; (SEND)
2 CEBER End bit error for response for non-auto-issued CMD's ;/
1? SCMDE Bad CMD-index in response of auto-issued CMD12 ;\STAT.16
0 RCMDE Bad CMD-index in response of non-auto-issued CMD's ;/(SCIX)
Unknown if/when/how the error bits can be reset/acknowledged.<br>
Note: CMD12 is STOP_TRANSMISSION (maybe sent after BLK_COUNT?).<br>
The four "auto-issued CMD12" bits exist for SD registers only (not SDIO).
SCMDE is probably in bit1 (though, official specs say bit0, which would be same
as RCMDE).
'''4004A36h - DSi: 0000 - SDCTL_CARD_INTERRUPT_CONTROL'''<br>
This does NOT seem to be implemented as described below on DSi.
4004A36h does seem to behave more like 4004836h, see there.
15-13 ? Unknown (zero on DSi)
12 CINT0 SDIO Interrupt Flag (0=none, 1=irq) (/IRQ aka Data1 pin)
11-9 ? Unknown (zero on DSi)
8 CIMSK0 SDIO Interrupt Mask (0=enable, 1=disable) (/IRQ aka Data1 pin)
7-0 ? Unknown (zero on DSi)
Acknowledge by writing CINT0=0, or CIMSK0=1, or hard reset (unlike as for other
SD/MMC interrupts, soft reset does not acknowlege this interrupt type?).