Difference between revisions of "I2C Bus"

Revision as of 21:18, 6 November 2010

Registers

NAME	ADDRESS	WIDTH
REG_I2CDATA	0x04004500	1
REG_I2CCNT	0x04004501	1

REG_I2CDATA

BIT	DESCRIPTION
0	R/W, clear for write, set for read
1	Start/device select bit?
2	Restart/device reselect bit?
3	?
4	SCL hold. When clear SCL is being held low, set when SCL is high. This bit must always be set(by reading CNT again) after writing REG_I2CCNT. This bit must be set when writing blocks of data(more than 1 byte) with bit0 clear.
5	SCL, toggle this for each loop iteration(in the loop execute the I2C WR code) with max 8 iterations where the loop exits successfully when bit 4 is set. This bit must be set when writing blocks of data(more than 1 byte) with bit0 clear.
6	Unknown, always set when writing to CNT?
7	Enable/busy

Protocol

Wait for the busy bit to clear. Write the device address to REG_I2CDATA, then write 0xc2(busy/enable, bit 6, and start bit 1 set) to REG_I2CCNT. Execute swiWaitByLoop for a device-specific duration, then write the register address to REG_I2CDATA, and write 0xc0 to REG_I2CCNT.(busy/enable and bit 6 set) Wait with swiWaitByLoop device duration, then write the data to REG_I2CDATA when writing. When reading, write the device address to REG_I2CDATA and write 0xc2 to REG_I2CCNT. When the delay value is zero, write 0xc1 | i<<5 to REG_I2CCNT, otherwise write 0xc0 | i<<5 to REG_I2CCNT, wait for busy to clear, delay, then write 0xc5 to REG_I2CCNT. For writing i is the loop i for iteration, for reading replace that with 1. When reading, read the data from REG_I2CCNT. Return a error if REG_I2CCNT bit 4 SCL hold is set, otherwise return normal.

I2C devices

I2C device table:

Device index in table	Device address	Device swiWaitByLoop delay	Device description
0	0x00	0x00	Camera0?
1	0x80	0x00	Camera1?
2	0x00	0x00	?
3	0x00	0x00	?
4	0x7A	0x180	Power management
5	0x78	0x00	?
6	0xA0	0x00	?

Power management addr 0x7A

When registers 0x70 and 0x11 are set to 1 in that order, a power cycle is done.

REGISTER	DESCRIPTION
0x11	System reset register 2.
0x12	MMC bus power? When value 1 is written here power to the MMC bus is disabled?(Enabling MMC power on hybrid cards will do nothing, since the bus is disabled via other registers.) Value 0 might enable MMC bus power?
0x31	Cameras' power? Value 0 turns off power to cameras? Values 1/2 activates a camera's power?
0x70	System reset register 1.

@@ Line 32: / Line 32: @@
 |-
 | 4
-| SCL hold. When clear SCL is being held low, set when SCL is high. This bit must always be set after writing REG_I2CCNT.
+| SCL hold. When clear SCL is being held low, set when SCL is high. This bit must always be set(by reading CNT again) after writing REG_I2CCNT. This bit must be set when writing blocks of data(more than 1 byte) with bit0 clear.
 |-
 | 5
-| SCL, toggle this for each loop iteration(in the loop execute the I2C WR code) with max 8 iterations where the loop exits successfully when bit 4 is set.
+| SCL, toggle this for each loop iteration(in the loop execute the I2C WR code) with max 8 iterations where the loop exits successfully when bit 4 is set. This bit must be set when writing blocks of data(more than 1 byte) with bit0 clear.
 |-
 | 6