NDMA: Difference between revisions

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!  WIDTH
!  WIDTH
|-
|-
REG_NDMA_MASTER_CNT
REG_NDMAGCNT
|  0x04004100
|  0x04004100
|  4
|  4
|-
|-
REG_NDMA_SRC(n)
REG_NDMASAD(n)
|  0x04004104 + (n*0x1c)
|  0x04004104 + (n*0x1c)
|  4
|  4
|-
|-
REG_NDMA_DEST(n)
REG_NDMADAD(n)
|  0x04004108 + (n*0x1c)
|  0x04004108 + (n*0x1c)
|  4
|  4
|-
|-
REG_NDMA_NUM0(n)
REG_NDMATCNT(n)
|  0x0400410c + (n*0x1c)
|  0x0400410c + (n*0x1c)
|  4
|  4
|-
|-
REG_NDMA_NUM1(n)
REG_NDMAWCNT(n)
|  0x04004110 + (n*0x1c)
|  0x04004110 + (n*0x1c)
|  4
|  4
|-
|-
REG_NDMA_14(n)
REG_NDMABCNT(n)
|  0x04004114 + (n*0x1c)
|  0x04004114 + (n*0x1c)
|  4
|  4
|-
|-
REG_NDMA_CLEAR(n)
REG_NDMAFDATA(n)
|  0x04004118 + (n*0x1c)
|  0x04004118 + (n*0x1c)
|  4
|  4
|-
|-
REG_NDMA_CNT(n)
REG_NDMACNT(n)
|  0x0400411c + (n*0x1c)
|  0x0400411c + (n*0x1c)
|  4
|  4
|}
|}


== REG_NDMA_MASTER_CNT ==
== REG_NDMAGCNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  BIT
!  BIT
!  DESCRIPTION
!  DESCRIPTION
|-
|-
15-0
19-16
|  ?
Cycle selection.
|-
16
Unknown, set when initialized by Arm7?
|-
|  17
|  Unknown, set when initialized by Arm9?
|-
|  18
|  Unknown, set when initialized by Arm7/Arm9?
|-
|  30-19
|  ?
|-
|-
|  31
|  31
Might be master NDMA enable, when initialized this is set?
DMA arbitration method. 0=Fixed method, 1=Round robin
|}
|}


== REG_NDMA_SRC ==
== REG_NDMASAD ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  BIT
!  BIT
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|-
|-
|  31-0
|  31-0
|  Source data address.
|  Source data address. Must be multiple of 4.
|}
|}
Like old DMA, REG_NDMA_SRC is copied to internal registers when written to.
Like old DMA, REG_NDMA_SRC is copied to internal registers when written to.


== REG_NDMA_DEST ==
== REG_NDMADAD ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  BIT
!  BIT
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|-
|-
|  31-0
|  31-0
|  Destination data address.
|  Destination data address. Must be multiple of 4.
|}
|}
Like old DMA, REG_NDMA_DEST is copied to internal registers when written to.
Like old DMA, REG_NDMA_DEST is copied to internal registers when written to.


== REG_NDMA_NUM0 ==
== REG_NDMATCNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  BIT
!  BIT
Line 93: Line 81:
|}
|}


== REG_NDMA_NUM1 ==
== REG_NDMAWCNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  BIT
!  BIT
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|}
|}


== REG_NDMA_14 ==
== REG_NDMABCNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  BIT
!  BIT
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|}
|}


Once the CNT bit31 enable bit is set, starting doing the DMA once the time units specified by this register elapses?
== REG_NDMAFDATA ==
 
== REG_NDMA_CLEAR ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  BIT
!  BIT
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|}
|}


== REG_NDMA_CNT ==
== REG_NDMACNT ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  BIT
!  BIT