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SD/MMC/SDIO Registers: Difference between revisions

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===4004802h/4004A02h - SD_CARD_PORT_SELECT===
===4004802h/4004A02h - SD_CARD_PORT_SELECT===
   15-11 Unknown/unused (appears to be always zero)
   15-11 Unknown/unused (appears to be always zero)
   10    Unknown (write: should be 1, read: usually/always 0)           (W?)
   10    Unknown (should be set on writing) (reads as zero)             (W)
   9     Unknown (write: should be 0, read: usually 1 for SD)            (R?)
   9-8  Unknown (Always 2 for SD/4004802h, always 1 for SDIO/4004A02h) (R)
  8    Unknown (write: should be 0, read: usually 1 for SDIO)         (R?)
   7-4  Unknown/unused (appears to be always zero)
   7-4  Unknown/unused (appears to be always zero)
   3-1  Unknown                                                        (R/W)
   3-1  Unknown                                                        (R/W)
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===4004828h/4004A28h - SD_CARD_OPTION - Card Option Setup===
===4004828h/4004A28h - SD_CARD_OPTION - Card Option Setup===
   15       Bus Width (0=4bit, 1=1bit)                       (R/W)
   15   undoc Bus Width (0=4bit, 1=1bit)                                   (R/W)
   14       Unknown (usually set)                             (R?)
   14   undoc Unknown (usually set)                                       (R?)
   13-9     Unknown/unused (appears to be always zero)
   13-9 0    Unknown/unused (appears to be always zero)
   8         Unknown (firmware toggles this after CLK change?) (W?)
   8   undoc Unknown (firmware tries to toggle this after CLK change?)   (W?)
   7-4       Unknown, maybe some 4bit timing/timeout value    (R/W)
   7-4 RTO  Data start/busy timout (2000h SHL 0..14, or 15=100h SDCLK's) (R/W)
   0-3       Unknown, maybe another 4bit timing/timeout value  (R/W)
   0-3 TO?  Unknown (another timeout, maybe for SDIO? in 32KHz units?)  (R/W)
Among others, this register should contain a 4bit timeout setting, "RTO[3:0] for SD (aka TO[3:0] for SDIO) timeout period for data start/busy bits, in the form of a multiple number of the SDCLK period."<br>
Among others, this register should contain a 4bit timeout setting, "RTO[3:0]
Unknown which "multiple numbers" that's referring to (probably some exponential/table values).<br>
for SD (aka TO[3:0] for SDIO) timeout period for data start/busy bits, in the
form of a multiple number of the SDCLK period." Unknown which "multiple
numbers" that's referring to (probably some exponential/table values).
Settings spotted on DSi are 40E0h,40EEh.
Settings spotted on DSi are 40E0h,40EEh.


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   SD_RESPONSE0-7            = zerofilled
   SD_RESPONSE0-7            = zerofilled
   SD_IRQ_STATUS0-1          = all IRQs flags acknowledged
   SD_IRQ_STATUS0-1          = all IRQs flags acknowledged
  SD_ERROR_DETAIL_STATUS0-1 = all bits cleared (except bit13/always set)
   SD_CARD_CLK_CTL          = bit 8 and 10 cleared
   SD_CARD_CLK_CTL          = bit 8 and 10 cleared
   SD_CARD_OPTION            = 40EEh
   SD_CARD_OPTION            = 40EEh
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   3-0    Unknown (0)
   3-0    Unknown (0)


===40048FAh - Can be 0004h..0007h (nonzero, unlike SDIO) (RESERVED6)===
===40048FAh - Can be 0007h (nonzero, unlike SDIO) (RESERVED6)===
   15-3  Unknown (0)
   15-3  Unknown (0)
   2      Unknown (usually set)                         (R)
   2      Unknown (1=normal, 0=data/read from card to fifo busy?)       (R)
   1-0    Unknown (0..3)                                (R/W? or rather R?)
   1-0    Unknown (0..3)                                (R/W? or rather R?)


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