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SD/MMC/SDIO Registers: Difference between revisions

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===4004800h/4004A00h - SD_CMD - Command and Response/Data Type (R/W)===
===4004800h/4004A00h - SD_CMD - Command and Response/Data Type (R/W)===
   15    undoc  Unknown/undoc  (read/write-able)
   15    undoc  Unknown/undoc  (read/write-able)
   14    undoc  Security Cmd   (0=Normal, 1=Whatever/Security) (sdio?)
   14    undoc  Security Cmd?  (0=Normal, 1=Whatever/Security?) (sdio?)
   13    undoc  Data Length    (0=Single Block, 1=Multiple Blocks)
   13    undoc  Data Length    (0=Single Block, 1=Multiple Blocks)
   12    undoc  Data Direction (0=Write, 1=Read)
   12    undoc  Data Direction (0=Write, 1=Read)
   11    NTDT    Data Transfer  (0=No data, 1=With data)
   11    NTDT    Data Transfer  (0=No data, 1=With data)
   10-8  REP2-0  Response Type  (0..2=Unknown/Reserved, 3=None, 4=48bit,
   10-8  REP2-0  Response Type  (0=Auto, 1..2=Unknown/Reserved, 3=None, 4=48bit,
                                 5=48bit+Busy, 6=136bit, 7=48bitOcrWithoutCRC7)
                                 5=48bit+Busy, 6=136bit, 7=48bitOcrWithoutCRC7)
   7-6  CMD1-0  Command Type  (0=CMD, 1=ACMD, 2..3=unknown, maybe GEN WR/RD?)
   7-6  CMD1-0  Command Type  (0=CMD, 1=ACMD, 2..3=unknown, maybe GEN WR/RD?)
   5-0  CIX    Command Index  (0..3Fh, command index)
   5-0  CIX    Command Index  (0..3Fh, command index)
Invalid values can cause ILA error (particulary on setting NTDT for CMD12, or for CMD's Response=None). ILA error will also occur if an old CMD is still busy.<br>
Setting Command Type to "ACMD" is automatically sending an APP_CMD prefix prior to the command number. For Multiple Blocks, the hardware supports automatically sending STOP_TRANSMISSION after the last block.<br>
DSi software is always writing just ZERO to bit11-6 though? Maybe the hardware does automatically know which SD/MMC CMDs and ACMDs have data? Or maybe data is always automatically transferred when receiving a data-startbit, or when writing to data register - and bits like NTDT would be needed only for things like proper data timeout handling?
DSi software is usually setting Response Type to "Auto", which is causing the hardware to use the correct response/data type for standard SD/MMC commands (bit11-13 are ignored/should be zero when using "Auto"; and maybe same for bit14-15?).<br>
One exception is that the DSi firmware isn't using "Auto" for SDIO commands (maybe the hardware isn't aware of them; or it's unable to distinguish between read/write direction of CMD53, which would require examining the command's PARAM bits).<br>
There might be subtle differences between some SD and MMC commands, unknown if/how "Auto" is working in that cases; unknown if there's a SD-or-MMC mode select bit for that purpose in some configuration register.<br>
Invalid values can cause ILA error (particulary on setting NTDT for CMD12, or for CMD's Response=None). ILA error will also occur if an old CMD is still busy.


===4004804h/4004A04h - SD_CMD_PARAM0-1 - Argument (32bit, 2 halfwords) (R/W)===
===4004804h/4004A04h - SD_CMD_PARAM0-1 - Argument (32bit, 2 halfwords) (R/W)===
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== DSi SD/MMC I/O Ports: Interrupt/Status ==
== DSi SD/MMC I/O Ports: Interrupt/Status ==


'''400481Ch - SD_IRQ_STATUS0-1 - Interrupt Status (R/ack)'''<br>
===400481Ch/4004A1Ch - SD_IRQ_STATUS0-1 - Interrupt Status (R/ack)===
'''4004A1Ch - SDIO_IRQ_STATUS0-1 - Interrupt Status (R/ack)'''<br>
===4004820h/4004A20h - SD_IRQ_MASK0-1 - Interrupt Mask (R/W)===
'''4004820h - SD_IRQ_MASK0-1 - Interrupt Mask (R/W)'''<br>
The IRQ_STATUS registers contain acknowledge-able IRQ Flags (those bits that that are maskable in IRQ_MASK register), as well as static read-only status bits without IRQ function (eg. WRPROTECT).
'''4004A20h - SDIO_IRQ_MASK0-1 - Interrupt Mask (R/W)'''<br>
*IRQ Flags/Write (0=Acknowledge, 1=No change)
The IRQ_STATUS registers contain acknowledge-able IRQ Flags (those bits that
*IRQ Flags/Read  (0=No IRQ, 1=IRQ)
that are maskable in IRQ_MASK register), as well as static read-only status
*IRQ Mask (0=Enable, 1=Disable) (8B7F031Dh when all IRQs disabled)
bits without IRQ function (eg. WRPROTECT).
   Bit Stat  Mask Function
* IRQ Flags/Write (0=Acknowledge, 1=No change)
   0  SREP  MREP CMDRESPEND    (response end) (or R1b: busy end)
* IRQ Flags/Read  (0=No IRQ, 1=IRQ)
   1  0    0     Unknown/unused (always 0)
* IRQ Mask (0=Enable, 1=Disable) (8B7F031Dh when all IRQs disabled)
   2  SRWA  MRWA DATAEND      (set after (last) data block end)
   Bit Stat  Mask   Function
   3  SCOT  MCOT CARD_REMOVE (0=No event, 1=Is/was newly ejected)      ;\
   0  SREP  MREP   CMDRESPEND    (response end) (or R1b: busy end)
   4  SCIN  MCIN CARD_INSERT (0=No event, 1=Is/was newly inserted)    ; SD
   1  0    0     Unknown/unused (always 0)
   5  undoc 0     SIGSTATE    (0=Ejected, 1=Inserted) (SDIO: always 1)  ; Slot
   2  SRWA  MRWA   DATAEND      (is NOT set? after data read/write end bit)
   6  0    0     Unknown/unused (always 0)                            ; Sw's
   3  SCOT  MCOT   CARD_REMOVE (0=No event, 1=Is/was newly ejected)      ;\DSi
   7  undoc 0     WRPROTECT  (0=Locked/Ejected, 1=Unlocked/HalfEjected);/
   4  SCIN  MCIN   CARD_INSERT (0=No event, 1=Is/was newly inserted)    ; SD
   8  undoc undoc CARD_REMOVE_A (0=No event, 1=High-to-Low occurred)   ;\SD
   5  undoc 0     SIGSTATE    (0=Ejected, 1=Inserted) (SDIO: always 1)  ; Card
   9  undoc undoc CARD_INSERT_A (0=No event, 1=Low-to-High óccurred)   ; Slot
   6  0    0     Unknown/unused (always 0)                            ; Slot
   10  undoc 0     SIGSTATE_A    (usually 1=High) ;also as so for SDIO   ;/Data3
   7  undoc 0     WRPROTECT  (0=Locked/Ejected, 1=Unlocked/HalfEjected);/
   11  0    0     Unknown/unused (always 0)
   8  undoc undoc CARD_REMOVE_A (always 0)   ;\maybe fixed state for
   12  0    0     Unknown/unused (always 0)
   9  undoc undoc CARD_INSERT_A (always 0)   ; DSi's onboard eMMC chip
   13  0    0     Unknown/unused (always 0)
   10  undoc 0     SIGSTATE_A    (always 1)   ;/(also fixed as so for SDIO)
   14  0    0     Unknown/unused (always 0)
   11  0    0     Unknown/unused (always 0)
   15  0    0     Unknown/unused (always 0)
   12  0    0     Unknown/unused (always 0)
   16  SCIX  MCIX CMD_IDX_ERR  Bad CMD-index in response      (RCMDE,SCMDE)
   13  0    0     Unknown/unused (always 0)
   17  SCRC  MCRC CRCFAIL      CRC response error (WCRCE,RCRCE,SCRCE,CCRCE)
   14  0    0     Unknown/unused (always 0)
   18  SEND  MEND STOPBIT_ERR  End bit error      (WEBER,REBER,SEBER,CEBER)
   15  0    0     Unknown/unused (always 0)
   19  SDTO  MDTO DATATIMEOUT  Data Timeout                (NRCS,NWCS,KBSY)
   16  SCIX  MCIX   CMD_IDX_ERR  Bad CMD-index in response      (RCMDE,SCMDE)
   20  SFOF  MFOF RXOVERFLOW    HOST tried write full
   17  SCRC  MCRC   CRCFAIL      CRC response error (WCRCE,RCRCE,SCRCE,CCRCE)
   21  SFUF  MFUF TXUNDERRUN    HOST tried read empty
   18  SEND  MEND   STOPBIT_ERR  End bit error      (WEBER,REBER,SEBER,CEBER)
   22  SCTO  MCTO CMDTIMEOUT    Response start-bit timeout        (NRS,NSR)
   19  SDTO  MDTO   DATATIMEOUT  Data Timeout                (NRCS,NWCS,KBSY)
   23  ???  0     Unknown/undoc (usually set) (zero after sending TX data?)
   20  SFOF  MFOF   RXOVERFLOW    HOST tried write full
   24  SBRE  MBRE RXRDY        (fifo not empty) (request data read)
   21  SFUF  MFUF   TXUNDERRUN    HOST tried read empty
   25  SBWE  MBWE TXRQ          (datafifoempty?) (request data write)
   22  SCTO  MCTO   CMDTIMEOUT    Response start-bit timeout        (NRS,NSR)
   26  0    0     Unknown/unused (always 0)
   23  1 ?  0     Unknown/undoc (usually set?)
   27  undoc undoc Unknown/undoc  (bit27 is mask-able in IRQ_MASK)
   24  SBRE  MBRE   RXRDY        (fifo not empty) (request data read)
   28  0    0     Unknown/unused (always 0)
   25  SBWE  MBWE   TXRQ          (datafifoempty?) (request data write)
   29  undoc 0    CMD_READY? (inverse of BUSY?) (unlike toshiba ILFSL/IFSMSK)
   26  0    0     Unknown/unused (always 0)
   30  undoc 0     CMD_BUSY
   27  undoc undoc Unknown/undoc  (bit27 is mask-able in IRQ_MASK)
   31  ILA  IMSK Illegal Command Access (old CMD still busy, or wrong NTDT)
   28  0    0     Unknown/unused (always 0)
Normally, IRQs should be acknowledged by writing "FLAGS=NOT X", whilst the firmware is using an unstable "FLAGS=FLAGS AND NOT X" read-modify-write function (accidentally acknowledging any IRQs that have newly occurred during that operation).
   29  1 ?   0      Unknown/undoc  (usually set?) (unlike toshiba ILFSL/IFSMSK)
   30  undoc 0     CMD_BUSY
   31  ILA  IMSK   Illegal Command Access (old CMD still busy, or wrong NTDT)
Acknowledge by STAT=0, or by MASK=1 (uh, really?), or by soft reset (SRST=0) or
hard reset.


 
===4004900h/4004B00h - SD_DATA32_IRQ===
'''4004900h - SD_DATA32_IRQ'''<br>
'''4004B00h - SDIO_DATA32_IRQ'''<br>
   15-13  Unknown/unused (appears to be always zero)
   15-13  Unknown/unused (appears to be always zero)
   12    Unknown (paired with bit9) (can be set)  IRQ enable ?!      (R/W?)
   12    DATA32_BUSY IRQ Enable  (0=Disable, 1=Enable)                 (R/W)
   11    Unknown (paired with bit8) (can be set)  IRQ enable ?!      (R/W?)
   11    DATA32_RXRDY IRQ Enable  (0=Disable, 1=Enable)                 (R/W)
   10    Unknown (read=0) write: (0=No change, 1=Clear Bit8,9) ?      (W?)
   10    DATA32 Abort/Flush FIFO? (0=No change, 1=Clear Bit8,9)         (W)
   9      Unknown (paired with bit12) (automatically cleared after...) (R?)
   9      DATA32_BUSY IRQ Flag    (auto cleared after...)               (R)
   8      Unknown (paired with bit11)                                 (R?)
   8      DATA32_RXRDY IRQ Flag    (auto cleared after...)               (R)
   7-2    Unknown (0)
   7-2    Unknown/unused (appears to be always zero)
   1      Unknown (can be set)  (autoclear bit8,9 on xfer end?)       (R/W?)
   1      Select 16bit/32bit Data Mode (0=DATA16, 1=DATA32, see 40048D8h) (R/W)
   0      Unknown (0)
   0      Unknown/unused (appears to be always zero)
Can be 1A02h, but changes to 1802h after reading from somewhere (maybe from
Can be 1A02h, but changes to 1802h after reading from somewhere (maybe from DATA32_FIFO?).<br>
DATA32_FIFO?).<br>
Bit8,9 are extra IRQ flags, the flags get set ONLY in DATA32 mode (not in DATA16 mode).
Bit8,9 seem to be whatever extra IRQ flags, the flags get set ONLY in DATA32
mode (not in DATA16 mode).
 


'''400482Ch - SD_ERROR_DETAIL_STATUS0-1 - Error Detail Status'''<br>
===400482Ch/4004A2Ch - SD_ERROR_DETAIL_STATUS0-1 - Error Detail Status===
'''4004A2Ch - SDIO_ERROR_DETAIL_STATUS0-1 - Error Detail Status'''<br>
This register contains extra info about the error bits in SD_IRQ_STATUS. The error bits (except bit13/always set) are automatically cleared when sending a new command by writing to SD_CMD.
   31-23 ?     Unknown/unused/undoc
   31-23 0     Unknown/unused (always zero)
   22    KBSY  Timeout for CRC status busy timeout                  ;\STAT.19
   22    KBSY  Timeout for CRC status busy                         ;\STAT.19
   21    NWCS  Timeout for CRC status timeout                      ; (SDTO)
   21    NWCS  Timeout for CRC status   (can occur for Data Write)  ; (SDTO)
   20    NRCS  Timeout for Data start-bit, or for Post Data Busy    ;/
   20    NRCS  Timeout for Data start-bit, or for Post Data Busy    ;/
   19-18 ?     Unknown/unused/undoc
   19-18 0     Unknown/unused (always zero)
   17    NRS    Response timeout for auto-issued CMD12              ;\STAT.22
   17    NRS    Response Timeout for auto-issued CMD12              ;\STAT.22
   16    NCR    Response timeout for non-auto-issued CMD's          ;/(SCTO)
   16    NCR    Response Timeout for non-auto-issued CMD's          ;/(SCTO)
   15-14 ?     Unknown/unused/undoc
   15-14 0     Unknown/unused (always zero)
   13    ??    Unknown/undoc (bit13 can be nonzero on DSi!)
   13    undoc  Unknown/undoc (always 1)                           ;-Always 1
   12    ?     Unknown/unused/undoc
   12    0     Unknown/unused (always zero)
   11    WCRCE  CRC error for Write CRC status for a write command  ;\
   11    WCRCE  CRC error for Write CRC status for a write command  ;\
   10    RCRCE  CRC error for read data                             ; STAT.17
   10    RCRCE  CRC error for Read Data                             ; STAT.17
   9    SCRCE  CRC error for a response for auto-issued CMD12      ; (SCRC)
   9    SCRCE  CRC error for a Response for auto-issued CMD12      ; (SCRC)
   8    CCRCE  CRC error for a response for non-auto-issued CMD's  ;/
   8    CCRCE  CRC error for a Response for non-auto-issued CMD's  ;/
   5    WEBER  End bit error for Write CRC status                  ;\
   5    WEBER  End bit error for Write CRC status                  ;\
   4    REBER  End bit error for read data                         ; STAT.18
   4    REBER  End bit error for Read Data                         ; STAT.18
   3    SEBER  End bit error for response for auto-issued CMD12    ; (SEND)
   3    SEBER  End bit error for Response for auto-issued CMD12    ; (SEND)
   2    CEBER  End bit error for response for non-auto-issued CMD's ;/
   2    CEBER  End bit error for Response for non-auto-issued CMD's ;/
   1?    SCMDE  Bad CMD-index in response of auto-issued CMD12      ;\STAT.16
   1?    SCMDE  Bad CMD-index in Response of auto-issued CMD12      ;\STAT.16
   0    RCMDE  Bad CMD-index in response of non-auto-issued CMD's  ;/(SCIX)
   0    RCMDE  Bad CMD-index in Response of non-auto-issued CMD's  ;/(SCIX)
Unknown if/when/how the error bits can be reset/acknowledged.<br>
Note: CMD12 is STOP_TRANSMISSION (automatically sent after BLK_COUNT blocks).<br>
Note: CMD12 is STOP_TRANSMISSION (maybe sent after BLK_COUNT?).<br>
The four "auto-issued CMD12" bits exist for SD registers only (not for SDIO, going by old toshiba datasheets; which may be wrong).
The four "auto-issued CMD12" bits exist for SD registers only (not SDIO).
SCMDE is probably in bit1 (though, official specs say bit0, which would be same as RCMDE).<br>
SCMDE is probably in bit1 (though, official specs say bit0, which would be same
Some error bits can be intentionally provoked: Bit8=1 when programming the controller to expect GET_STATUS to return a 136bit response. Bit16=1 when sending GET_CID in "tran" state. Bit20=1 when sending GET_STATUS configured to expect a data/read reply. Bit21=1 when sending GET_STATUS configured to expect a data/write block (and with actually sending a data block to it).
as RCMDE).
 
 
'''4004A36h - DSi: 0000 - SDCTL_CARD_INTERRUPT_CONTROL'''<br>
This does NOT seem to be implemented as described below on DSi.
4004A36h does seem to behave more like 4004836h, see there.
  15-13  ?      Unknown (zero on DSi)
  12    CINT0  SDIO Interrupt Flag (0=none, 1=irq)      (/IRQ aka Data1 pin)
  11-9  ?      Unknown (zero on DSi)
  8      CIMSK0 SDIO Interrupt Mask (0=enable, 1=disable) (/IRQ aka Data1 pin)
  7-0    ?      Unknown (zero on DSi)
Acknowledge by writing CINT0=0, or CIMSK0=1, or hard reset (unlike as for other
SD/MMC interrupts, soft reset does not acknowlege this interrupt type?).


== DSi SD/MMC I/O Ports: Control ==
== DSi SD/MMC I/O Ports: Control Registers ==


'''4004802h - SD_CARD_PORT_SELECT           (0201h)'''<br>
===4004802h/4004A02h - SD_CARD_PORT_SELECT===
'''4004A02h - SDIO_CARD_PORT_SELECT          (0100h)'''<br>
   15-11 Unknown/unused (appears to be always zero)
   15-11 Unknown/unused (appears to be always zero)
   10    Unknown (write: should be 1, read: usually/always 0)   (W?)
   10    Unknown (should be set on writing) (reads as zero)             (W)
   9     Unknown (write: should be 0, read: usually 1 for SD)
   9-8  Unknown (Always 2 for SD/4004802h, always 1 for SDIO/4004A02h)  (R)
  8    Unknown (write: should be 0, read: usually 1 for SDIO)
   7-4  Unknown/unused (appears to be always zero)
   7-4  Unknown/unused (appears to be always zero)
   3-1  Unknown (R/W)
   3-1  Unknown                                                         (R/W)
   0    Port Select (0=SD Card Slot, 1=Onboard eMMC) (for SDIO: Unknown)
   0    Port Select (0=SD Card Slot, 1=Onboard eMMC) (for SDIO: Unknown)(R/W)
Known written values are 0400h and 0401h (SD). However known read values are
0201h (SD) and 0100h (SDIO).
 


'''4004828h - DSi: 40E0 - SD_CARD_OPTION - Memory Card Option Setup'''<br>
===4004828h/4004A28h - SD_CARD_OPTION - Card Option Setup===
'''4004A28h - DSi: 40EE - SDIO_CARD_OPTION - Card Option Setup'''<br>
   15   undoc Bus Width (0=4bit, 1=1bit)                                  (R/W)
   15       Bus Width (0=4bit, 1=1bit)
   14   undoc Unknown (usually set)                                        (R?)
   14       Unknown (usually set)
   13-9 0    Unknown/unused (appears to be always zero)
   13-8      Unknown/unused (appears to be always zero)
  8    undoc Unknown (firmware tries to toggle this after CLK change?)    (W?)
   7-4       Unknown, maybe some 4bit timing/timeout value
   7-4 RTO  Data start/busy timout (2000h SHL 0..14, or 15=100h SDCLK's) (R/W)
   0-3       Unknown, maybe another 4bit timing/timeout value
   0-3 TO?  Unknown (another timeout, maybe for SDIO? in 32KHz units?)  (R/W)
Settings spotted on DSi are 40E0h,40EEh.<br>
Among others, this register should contain a 4bit timeout setting, "RTO[3:0]
Among others, this register should contain a 4bit timeout setting, "RTO[3:0]
for SD (aka TO[3:0] for SDIO) timeout period for data start/busy bits, in the
for SD (aka TO[3:0] for SDIO) timeout period for data start/busy bits, in the
form of a multiple number of the SDCLK period."<br>
form of a multiple number of the SDCLK period." Unknown which "multiple
Maybe also selects transfer CLK rate, or whatever.
numbers" that's referring to (probably some exponential/table values).
Settings spotted on DSi are 40E0h,40EEh.


===4004824h/4004A24h - SD_CARD_CLK_CTL Card Clock Control===
  15-11 Unknown (always 0)  ;unlike Toshiba: no HCLK divider-disable in bit15)
  10    Unknown (0=Normal, 1=Unknown, doesn't affect SDCLK output?)      (R/W)
  9    Unknown (0=Normal, 1=Unknown, freezes SDCLK output?)              (R/W)
  8    SDCLK Enable (0=Force SDCLK=LOW, 1=Output SDCLK=HCLK/n)          (R/W)
  7-0  HCLK Div (0,1,2,4,8,16,32,64,128 = Div2,4,8,16,32,64,128,256,512) (R/W)
The DSi uses HCLK=33.513982 MHz, the SDCLK pin can range from HCLK/512=65kHz to HCLK/2=16.757MHz, max transfer rate would be thus 8MByte/s in 4bit mode.<br>
Card detection should be done at a low clock rate. For SD/MMC, the DSi starts with HCLK/128, and uses the clock specified in CSD register after detection (when extracting bits from CSD: mind the different 120bit-without-CRC vs 128bit-with-CRC notations). For SDIO, the DSi starts with HCLK/256, and switches to HCLK/2 after reading SDIO Bus Speed register (Function0:00013h).<br>
The SDCLK pins are permanently pulsed, even for devices deselected via SD_CARD_PORT_SELECT.0, and even if no CMD or DATA is being transferred. However, the DSi firmware is usually stopping SDCLK via Bit8=0 when not accessing SD/MMC (doing so may reduce noise and power consumption).<br>
Trying to set bit9, or to set more than one bit in bit7-0 will freeze the SDCLK output (in this case SDCLK may get stuck HIGH or LOW, unlike Bit8=0 which forces LOW).


'''4004834h - DSi: 0000 - SD_TRANSACTION_CTL - Transaction Control'''<br>
===4004808h/4004A08h - SD_STOP_INTERNAL_ACTION===
'''4004A34h - DSi: 0000 - SDIO_TRANSACTION_CTL - Transaction Control'''<br>
   15-9  Unknown/unused (appears to be always zero)
   15-10 Unknown/unused (appears to be always zero)
   8      Auto-Stop (1=Automatically send CMD12 after BLK_COUNT blocks)  (R/W)
   9-8  Unknown
   7-1    Unknown/unused (appears to be always zero)
   7-3  Unknown/unused (appears to be always zero)
   0      Unknown                                                       (R/W)
   2    Unknown
Stop whatever internal action for whatever purpose in whatever situation?<br>
  1    Unknown/unused (appears to be always zero)
Existing code does set bit8 (prior to changing SD_DATA16_BLK_COUNT).<br>
  0    Unknown
Existing code does clear bit0 (alongsides with IRQ enable/acknowlege or so).<br>
Maybe also selects transfer CLK rate, or whatever.
 


'''40048E0h - DSi: 0007 - SD_SOFT_RESET - Software Reset'''<br>
===40048E0h/4004AE0h - SD_SOFT_RESET - Software Reset===
'''4004AE0h - DSi: 0006 - SDIO_SOFT_RESET - Software Reset'''<br>
   15-3 Unknown/unused (appears to be always zero)
   15-3 Unknown/unused (appears to be always zero)
   2   ?   Unknown (can be nonzero on DSi)
   2    Unknown (always 1)                                            (R?)
   1   ?   Unknown (can be nonzero on DSi)
   1    Unknown (always 1) (though firmware tries to toggle this bit) (R?)
   0    SRST Soft Reset (0=Reset, 1=Release)
   0    SRST Soft Reset (0=Reset, 1=Release)                          (R/W)
Software should apply reset after sensing card insertion/removal, and
Software should apply reset after sensing card insertion/removal, and (thereafter) release reset in case of card insertion. Software reset does acknowledge all IRQs (except that from SDIO /IRQ pin?), and does probably also reinitialize some other registers.<br>
(thereafter) release reset in case of card insertion. Software reset does
Clearing bit0 does force following settings (while and as long as Bit0=0):
acknowledge all IRQs (except that from SDIO /IRQ pin?), and does probably also
  SD_STOP_INTERNAL_ACTION  = 0000h
reinitialize some other registers.
  SD_RESPONSE0-7            = zerofilled
  SD_IRQ_STATUS0-1          = all IRQs flags acknowledged
  SD_ERROR_DETAIL_STATUS0-1 = all bits cleared (except bit13/always set)
  SD_CARD_CLK_CTL          = bit 8 and 10 cleared
  SD_CARD_OPTION            = 40EEh
  SD_CARD_INTERRUPT_CONTROL = 0000h
All other registers seem to be left unaffected (including the the extra IRQ flags in 4004900h); though there may be some further hidden effects (like aborting transfers or resetting internal registers).<br>
Note: The DSi firmware does issue reset by toggling both bit0 and bit1, although bit1 does seem to be read-only (always 1), and trying to clear that bit doesn't seem to have any effect at all.


== DSi SD/MMC I/O Ports: Unknown/Unused Registers ==


'''4004808h - DSi: 0100 - SDCTL_STOP_INTERNAL_ACTION'''<br>
===40048F6h/4004AF6h - Firmware tests bit0 (but, always 0?) (RESERVED4)===
  15-9  Unknown/unused (appears to be always zero)
   15-1   Unknown (0)
  8      Unknown (1=Enable automatic sending of CMD12 after BLK_COUNT blocks?)
   0      Unknown (tested by firmware) (usually 0)      (R)
   7-1   Unknown/unused (appears to be always zero)
   0      Unknown
Stop whatever internal action for whatever purpose in whatever situation?<br>
Existing code does set bit8 (prior to changing SD_DATA16_BLK_COUNT).<br>
Existing code does clear bit0 (alongsides with IRQ enable/acknowlege or so).


===4004836h/4004A36h - SD_CARD_INTERRUPT_CONTROL ---- USED by SDIO===
4004A36h is used in SDIO IRQ handler.<br>
On DSi, this register looks as so:
  15-2  Unknown (0)
  1      Unknown (gets set automatically after 2 seconds?) (and also R/W ?)
  0      Unknown (usually always 0) (tested by firmware?)              (R?)
Whilst old toshiba datasheets specify it as so:
  15-13  ?      Unknown (zero on DSi)
  12    CINT0  SDIO Interrupt Flag (0=none/ack, 1=irq)  (/IRQ aka Data1 pin)
  11-9  ?      Unknown (zero on DSi)
  8      CIMSK0 SDIO Interrupt Mask (0=enable, 1=disable) (/IRQ aka Data1 pin)
  7-0    ?      Unknown (zero on DSi)
Acknowledge by writing CINT0=0, or CIMSK0=1 (uh, really?), or hard reset (unlike as for other SD/MMC interrupts, soft reset does not acknowlege this interrupt type?).


'''4004824h - DSi: 0000 - DSi: Used? - SDCTL_CARD_CLK_CTL Card Clock Control'''<br>
===4004838h/4004A38h - SDCTL_CLK_AND_WAIT_CTL ---- USED by SDIO===
Can be max 07FFh on DSi... ie. bit15 CANNOT be set?
4004A38h is used in SDIO IRQ handler.<br>
   15     Disable HCLK divider (0=SDCLK selected via bit7-0, 1=SDCLK=HCLK)
On DSi, this register looks as so (usually zero):
  14-10 Unknown (zero on DSi)
   15-14  Unknown (usually 0)                           (R/W)
  9      Unknown (set in some cases on DSi)
   13-3  Unknown (0)
   8      Unknown (1=Start Clock, or Apply Clock Change, or so?)
   2-0    Unknown (usually 0)                           (R/W)
   7-0    HCLK Div (0,1,2,4,8,10h,20h,40h,80h = Div2,4,8,16,32,64,128,256,512)
Whilst old toshiba datasheets specify it as so:
Clock supply to SD Card<br>
  15-0   Unknown (bit8 should be set after SD_CARD_CLK_CTL change?)
The SDCLK signal is used for a provision of SD Memory Card or SDIO Card. Please
refer to the following setting for enabling the SDCLK output.
(1) Set Stop Clock Control Register (Config Offset:40h) to 1Fh.
(2) Set D0 of SD Software Reset Register (Offset:0E0h) to 1b.
(3) Set D7-0 of SD Card Clock Control Register (Offset:024h). These bits
    are used for setting the frequency of SDCLK.
      80h : SDCLK=HCLK/512
      40h : SDCLK=HCLK/256
      20h : SDCLK=HCLK/128
      10h : SDCLK=HCLK/64
      08h : SDCLK=HCLK/32
      04h : SDCLK=HCLK/16
      02h : SDCLK=HCLK/8
      01h : SDCLK=HCLK/4
      00h : SDCLK=HCLK/2
    In addition, TC6387XB holds a function that SDCLK can have same
    frequency as HCLK. In this case, D7-0 settings of SD Card Clock Control
    Register (Offset:024h) becomes invalid setting.
    * Set D0 of Clock Mode Register (Config Offset:42h) to 1b.
    * Set D15 of SD Card Clock Control Register (Offset:024h) to 1b.
    Please attend that the specification of SDCLK is max.25MHz at the case
    of SD Card and is max.20MHz at the case of MultiMedia Card.
(4) D8 of SD Card Clock Control Register (Offset:024h) to 1b.
(5) D8 of Clock & Wait Control Register (Offset:138h) to 1b.
On the DSi, HCLK seems to be 33.513982 MHz.


Below registers don't seem to be used by existing software...


'''4004x38h - DSi: 0000 - SDCTL_CLK_AND_WAIT_CTL'''<br>
===4004834h/4004A34h - SD_TRANSACTION_CTL - Transaction Control===
   15-0   Unknown (zero on DSi)
   15-10 Unknown/unused (appears to be always zero)
Maybe transfer CLK rate, or some master clock control for the clock input.
  9-8  Unknown                                    (R/W)
  7-3  Unknown/unused (appears to be always zero)
  2    Unknown                                    (R/W)
   1    Unknown/unused (appears to be always zero)
  0    Unknown                                    (R/W)


===40048F2h/4004AF2h - Can be 0003h===
  15-2  Unknown (0)
  1-0    Unknown (0..3)                                (R/W)


'''4004x3Ah - DSi: 0000 - SDCTL_SDIO_HOST_INFORMATION'''<br>
===40048F4h/4004AF4h - Can be 0770h===
'''4004x3Ch - DSi: 0000 - SDCTL_ERROR_CONTROL'''<br>
  15-11  Unknown (0)
'''4004x3Eh - DSi: 0000 - SDCTL_SDLED_CONTROL - LED Control (TC6387XB only)'''<br>
  10-8  Unknown (0..7)                                (R/W)
   15-0   Unknown (zero on DSi)
  7      Unknown (0)
  6-4    Unknown (0..7)                                (R/W)
   3-0   Unknown (0)


===40048FAh - Can be 0007h (nonzero, unlike SDIO) (RESERVED6)===
  15-3  Unknown (0)
  2      Unknown (1=normal, 0=data/read from card to fifo busy?)      (R)
  1-0    Unknown (0..3)                                (R/W? or rather R?)


'''40048E2h - DSi: 0009 - SDCTL_RESERVED2 (TC6371AF:CORE_REV)'''<br>
===40048FCh/4004AFCh - Can be 0024h..00FFh? (RESERVED7)===
'''40048E6h - DSi: 0000 - SDCTL_RESERVED3 (TC6371AF:BUF_ADR)'''<br>
===40048FEh/4004AFEh - Can be 0024h..00FFh? (RESERVED8 / TC6371AF:Revision)===
'''40048E8h - DSi: 0000 - UNDOC/UNUSED (TC6371AF:Resp_Header)'''<br>
  15-8   Unknown (0)
'''40048F6h - DSi: 0000 - SDCTL_RESERVED4 --- used by DSi !!!'''<br>
   7-0    Can be 24h..FFh      parts (R) and parts (R/W)?
'''40048F8h - DSi: 0004 - SDCTL_RESERVED5   <-- DSi: SD only (not SDIO)'''<br>
'''40048FAh - DSi: 0007 - SDCTL_RESERVED6   <-- DSi: SD only (not SDIO)'''<br>
'''40048FCh - DSi: 00FC - SDCTL_RESERVED7'''<br>
'''40048FEh - DSi: 00FF - SDCTL_RESERVED8 (TC6371AF:Revision)'''<br>
'''4004xE2h - DSi: 0000 - SDCTL_RESERVED9'''<br>
'''4004xF0h - DSi: 0000 - SDCTL_RESERVED10'''<br>
'''4004836h - DSi: 0002 - UNDOC!  (bit1 can be set, other bits always 0)'''<br>
  15-0  Unknown


===Unused Registers with Fixed value (all bits read-only, or write-only)===
  400482Ah/4004A2Ah 2    Fixed always zero?
  4004832h/4004A32h 2    Fixed always zero?  ;(TC6371AF:BUF1 Data MSBs?)
  400483Ah/4004A3Ah 2    Fixed always zero?  ;(SDCTL_SDIO_HOST_INFORMATION)
  400483Ch/4004A3Ch 2    Fixed always zero?  ;(SDCTL_ERROR_CONTROL)
  400483Eh/4004A3Eh 2    Fixed always zero?  ;(TC6387XB: LED_CONTROL)
  4004840h/4004A40h 2    Fixed always 003Fh?
  4004842h/4004A42h 2    Fixed always 002Ah?
  4004844h/4004A44h 6Eh  Fixed always zerofilled?
  40048B2h/4004AB2h 2    Fixed always FFFFh?
  40048B4h/4004AB4h 6    Fixed always zerofilled?
  40048BAh/4004ABAh 2    Fixed always 0200h?
  40048BCh/4004ABCh 1Ch  Fixed always zerofilled?
  40048DAh/4004ADAh 6    Fixed always zerofilled?
  40048E2h/4004AE2h 2    Fixed always 0009h?  ;(RESERVED2/9, TC6371AF:CORE_REV)
  40048E4h/4004AE4h 2    Fixed always zero?
  40048E6h/4004AE6h 2    Fixed always zero?  ;(RESERVED3, TC6371AF:BUF_ADR)
  40048E8h/4004AE8h 2    Fixed always zero?  ;(TC6371AF:Resp_Header)
  40048EAh/4004AEAh 6    Fixed always zerofilled?
  40048F0h/4004AF0h 2    Fixed always zero?  ;(RESERVED10)
  40048F8h          2    Fixed always 0004h?  (unlike SDIO) (RESERVED5)
  4004AF8h          2    Fixed always zero?    (unlike SD)  (RESERVED5)
  4004AFAh          2    Fixed always zero?    (unlike SD)  (RESERVED6)
  4004902h/4004B02h 2    Fixed always zero?
  4004906h/4004B06h 2    Fixed always zero?
  400490Ah/4004B0Ah 2    Fixed always zero?
  4004910h/4004B10h F0h  Fixed always zerofilled?


'''4004838h/4004A38h - DSi: C007 - UNDOC!'''<br>
== Links ==
'''4004840h/4004A40h - DSi: 003F - UNDOC?'''<br>
* [http://gbatemp.net/threads/dsi-reverse-engineering-sd-mmc-sdio-registers.395787/ DSi SD/MMC reverse engineering thread in gbatemp forum]
'''4004842h/4004A42h - DSi: 002A - UNDOC?'''<br>
'''40048B2h/4004AB2h - DSi: FFFF - UNDOC?'''<br>
'''40048BAh/4004ABAh - DSi: 0200 - UNDOC?'''<br>
'''40048F4h/4004AF4h - DSi: 0700 - UNDOC!'''<br>
  15-0  Unknown
Retrieved from "https://dsibrew.org/wiki/SD/MMC/SDIO_Registers"