SD/MMC/SDIO Registers: Difference between revisions

Line 192:

===400482Ch/4004A2Ch - SD_ERROR_DETAIL_STATUS0-1 - Error Detail Status===

31-23 ? Unknown/unused~~/undoc~~

This register contains extra info about the error bits in SD_IRQ_STATUS. The error bits (except bit13/always set) are automatically cleared when sending a new command by writing to SD_CMD.

22 KBSY Timeout for CRC status busy ~~timeout~~ ;\STAT.19

31-23 0 Unknown/unused (always zero)

21 NWCS Timeout for CRC status ~~timeout~~ ; (SDTO)

22 KBSY Timeout for CRC status busy ;\STAT.19

21 NWCS Timeout for CRC status (can occur for Data Write) ; (SDTO)

20 NRCS Timeout for Data start-bit, or for Post Data Busy ;/

19-18 ? Unknown/unused~~/undoc~~

19-18 0 Unknown/unused (always zero)

17 NRS Response ~~timeout~~ for auto-issued CMD12 ;\STAT.22

17 NRS Response Timeout for auto-issued CMD12 ;\STAT.22

16 NCR Response ~~timeout~~ for non-auto-issued CMD's ;/(SCTO)

16 NCR Response Timeout for non-auto-issued CMD's ;/(SCTO)

15-14 ? Unknown/unused~~/undoc~~

15-14 0 Unknown/unused (always zero)

13 ?? Unknown/undoc ~~(bit13 can be nonzero on DSi!)~~ (always 1~~?) (R?~~)

13 undoc Unknown/undoc (always 1) ;-Always 1

12 ? Unknown/unused~~/undoc~~

12 0 Unknown/unused (always zero)

11 WCRCE CRC error for Write CRC status for a write command ;\

10 RCRCE CRC error for ~~read data~~ ; STAT.17

10 RCRCE CRC error for Read Data ; STAT.17

9 SCRCE CRC error for a ~~response~~ for auto-issued CMD12 ; (SCRC)

9 SCRCE CRC error for a Response for auto-issued CMD12 ; (SCRC)

8 CCRCE CRC error for a ~~response~~ for non-auto-issued CMD's ;/

8 CCRCE CRC error for a Response for non-auto-issued CMD's ;/

5 WEBER End bit error for Write CRC status ;\

4 REBER End bit error for ~~read data~~ ; STAT.18

4 REBER End bit error for Read Data ; STAT.18

3 SEBER End bit error for ~~response~~ for auto-issued CMD12 ; (SEND)

3 SEBER End bit error for Response for auto-issued CMD12 ; (SEND)

2 CEBER End bit error for ~~response~~ for non-auto-issued CMD's ;/

2 CEBER End bit error for Response for non-auto-issued CMD's ;/

1? SCMDE Bad CMD-index in ~~response~~ of auto-issued CMD12 ;\STAT.16

1? SCMDE Bad CMD-index in Response of auto-issued CMD12 ;\STAT.16

0 RCMDE Bad CMD-index in ~~response~~ of non-auto-issued CMD's ;/(SCIX)

0 RCMDE Bad CMD-index in Response of non-auto-issued CMD's ;/(SCIX)

~~Unknown if/when/how the error bits can be reset/acknowledged. ~~

Note: CMD12 is STOP_TRANSMISSION (automatically sent after BLK_COUNT blocks).

Note: CMD12 is STOP_TRANSMISSION (~~maybe~~ sent after BLK_COUNT?).

The four "auto-issued CMD12" bits exist for SD registers only (not for SDIO, going by old toshiba datasheets; which may be wrong).

The four "auto-issued CMD12" bits exist for SD registers only (not SDIO).~~ ~~

SCMDE is probably in bit1 (though, official specs say bit0, which would be same as RCMDE).

SCMDE is probably in bit1 (though, official specs say bit0, which would be same as RCMDE).

Some error bits can be intentionally provoked: Bit8=1 when programming the controller to expect GET_STATUS to return a 136bit response. Bit16=1 when sending GET_CID in "tran" state. Bit20=1 when sending GET_STATUS configured to expect a data/read reply. Bit21=1 when sending GET_STATUS configured to expect a data/write block (and with actually sending a data block to it).

== DSi SD/MMC I/O Ports: Control Registers ==

@@ Line 192: / Line 192: @@
 ===400482Ch/4004A2Ch - SD_ERROR_DETAIL_STATUS0-1 - Error Detail Status===
--23 ?      Unknown/unused/undoc
+This register contains extra info about the error bits in SD_IRQ_STATUS. The error bits (except bit13/always set) are automatically cleared when sending a new command by writing to SD_CMD.
-    KBSY   Timeout for CRC status busy timeout                  ;\STAT.19
+-23 0      Unknown/unused (always zero)
-    NWCS   Timeout for CRC status timeout                       ; (SDTO)
+    KBSY   Timeout for CRC status busy                          ;\STAT.19
+    NWCS   Timeout for CRC status   (can occur for Data Write)  ; (SDTO)
     NRCS   Timeout for Data start-bit, or for Post Data Busy    ;/
--18 ?      Unknown/unused/undoc
+-18 0      Unknown/unused (always zero)
-    NRS    Response timeout for auto-issued CMD12               ;\STAT.22
+    NRS    Response Timeout for auto-issued CMD12               ;\STAT.22
-    NCR    Response timeout for non-auto-issued CMD's           ;/(SCTO)
+    NCR    Response Timeout for non-auto-issued CMD's           ;/(SCTO)
--14 ?      Unknown/unused/undoc
+-14 0      Unknown/unused (always zero)
-    ??     Unknown/undoc (bit13 can be nonzero on DSi!) (always 1?) (R?)
+    undoc  Unknown/undoc  (always 1)                            ;-Always 1
-    ?      Unknown/unused/undoc
+    0      Unknown/unused (always zero)
     WCRCE  CRC error for Write CRC status for a write command   ;\
-    RCRCE  CRC error for read data                              ; STAT.17
+    RCRCE  CRC error for Read Data                              ; STAT.17
-     SCRCE  CRC error for a response for auto-issued CMD12       ; (SCRC)
+     SCRCE  CRC error for a Response for auto-issued CMD12       ; (SCRC)
-     CCRCE  CRC error for a response for non-auto-issued CMD's   ;/
+     CCRCE  CRC error for a Response for non-auto-issued CMD's   ;/
      WEBER  End bit error for Write CRC status                   ;\
-     REBER  End bit error for read data                          ; STAT.18
+     REBER  End bit error for Read Data                          ; STAT.18
-     SEBER  End bit error for response for auto-issued CMD12     ; (SEND)
+     SEBER  End bit error for Response for auto-issued CMD12     ; (SEND)
-     CEBER  End bit error for response for non-auto-issued CMD's ;/
+     CEBER  End bit error for Response for non-auto-issued CMD's ;/
-?    SCMDE  Bad CMD-index in response of auto-issued CMD12       ;\STAT.16
+?    SCMDE  Bad CMD-index in Response of auto-issued CMD12       ;\STAT.16
-     RCMDE  Bad CMD-index in response of non-auto-issued CMD's   ;/(SCIX)
+     RCMDE  Bad CMD-index in Response of non-auto-issued CMD's   ;/(SCIX)
-Unknown if/when/how the error bits can be reset/acknowledged.<br>
+Note: CMD12 is STOP_TRANSMISSION (automatically sent after BLK_COUNT blocks).<br>
-Note: CMD12 is STOP_TRANSMISSION (maybe sent after BLK_COUNT?).<br>
+The four "auto-issued CMD12" bits exist for SD registers only (not for SDIO, going by old toshiba datasheets; which may be wrong).
-The four "auto-issued CMD12" bits exist for SD registers only (not SDIO).<br>
+SCMDE is probably in bit1 (though, official specs say bit0, which would be same as RCMDE).<br>
-SCMDE is probably in bit1 (though, official specs say bit0, which would be same as RCMDE).
+Some error bits can be intentionally provoked: Bit8=1 when programming the controller to expect GET_STATUS to return a 136bit response. Bit16=1 when sending GET_CID in "tran" state. Bit20=1 when sending GET_STATUS configured to expect a data/read reply. Bit21=1 when sending GET_STATUS configured to expect a data/write block (and with actually sending a data block to it).
 == DSi SD/MMC I/O Ports: Control Registers ==