NDMA: Difference between revisions

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|  Destination data address. Must be multiple of 4.
|  Destination data address. Must be multiple of 4.
|}
|}
Like old DMA, REG_NDMA_DEST is copied to internal registers when written to.
Like old DMA, REG_NDMADAD is copied to internal registers when written to.


== REG_NDMATCNT ==
== REG_NDMATCNT ==
Line 77: Line 77:
!  DESCRIPTION
!  DESCRIPTION
|-
|-
|  31-0
|  27-0
|  Number of bytes to copy/write, see REG_NDMA_CNT bit28.
|  Total number of words transferred.
|}
|}


Line 86: Line 86:
!  DESCRIPTION
!  DESCRIPTION
|-
|-
|  31-0
|  23-0
|  Number of bytes to copy/write, see REG_NDMA_CNT bit28.
|  Total number of words to transfer.
|}
|}


Line 95: Line 95:
!  DESCRIPTION
!  DESCRIPTION
|-
|-
|  31-0
|  15-0
|  Time related?
|  Interval timer.
|-
|  17-16
|  Prescaler. 0=System freq, 1=1/4th freq, 2=1/16th freq, 3=1/64th freq.
|}
|}


Line 105: Line 108:
|-
|-
|  31-0
|  31-0
|  Value to write to destination instead of copying when REG_NDMA_CNT bit13 and bit14 are set.
|  Fill data.
|}
|}


Line 113: Line 116:
!  DESCRIPTION
!  DESCRIPTION
|-
|-
|  10-0
|  11-10
|  ?
|  Destination address update method.
|-
|-
|  11
|  12
|  Fixed destination address when set.
|  Destination address reload flag.
|-
|-
|  12
|  14-13
|  ?
|  Source address update method.
|-
|-
|  13
|  15
|  When set clear data with the value REG_NDMA_CLEAR instead of copying.
|  Source address reload flag.
|-
|-
|  14
|  19-16
|  Fixed source address when set.
|  Block transfer word count.
|-
|-
|  27-15
|  27-24
|  ?
|  Startup mode.
|-
|-
|  28
|  28
|  Set when REG_NDMA_NUM0 was set, clear when REG_NDMA_NUM1 was set.
|  Immediate mode.
|-
|  29
|  Repeating mode.
|-
|-
|  30
|  30
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|-
|-
|  31
|  31
|  Enable/busy
|  Enable/busy flag.
|}
|}

Revision as of 05:23, 25 November 2010

Registers

There's 4 NDMA channels. Arm7/Arm9 have separate NDMA.

NAME ADDRESS WIDTH
REG_NDMAGCNT 0x04004100 4
REG_NDMASAD(n) 0x04004104 + (n*0x1c) 4
REG_NDMADAD(n) 0x04004108 + (n*0x1c) 4
REG_NDMATCNT(n) 0x0400410c + (n*0x1c) 4
REG_NDMAWCNT(n) 0x04004110 + (n*0x1c) 4
REG_NDMABCNT(n) 0x04004114 + (n*0x1c) 4
REG_NDMAFDATA(n) 0x04004118 + (n*0x1c) 4
REG_NDMACNT(n) 0x0400411c + (n*0x1c) 4

REG_NDMAGCNT

BIT DESCRIPTION
19-16 Cycle selection.
31 DMA arbitration method. 0=Fixed method, 1=Round robin

REG_NDMASAD

BIT DESCRIPTION
31-0 Source data address. Must be multiple of 4.

Like old DMA, REG_NDMA_SRC is copied to internal registers when written to.

REG_NDMADAD

BIT DESCRIPTION
31-0 Destination data address. Must be multiple of 4.

Like old DMA, REG_NDMADAD is copied to internal registers when written to.

REG_NDMATCNT

BIT DESCRIPTION
27-0 Total number of words transferred.

REG_NDMAWCNT

BIT DESCRIPTION
23-0 Total number of words to transfer.

REG_NDMABCNT

BIT DESCRIPTION
15-0 Interval timer.
17-16 Prescaler. 0=System freq, 1=1/4th freq, 2=1/16th freq, 3=1/64th freq.

REG_NDMAFDATA

BIT DESCRIPTION
31-0 Fill data.

REG_NDMACNT

BIT DESCRIPTION
11-10 Destination address update method.
12 Destination address reload flag.
14-13 Source address update method.
15 Source address reload flag.
19-16 Block transfer word count.
27-24 Startup mode.
28 Immediate mode.
29 Repeating mode.
30 IRQ enable
31 Enable/busy flag.
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