Difference between revisions of "ARM9 SWI Functions"
Jump to navigation
Jump to search
Hallowizer (talk | contribs) (added SVC_SHA1GetHash from comparing IOSC code) |
|||
| (5 intermediate revisions by 2 users not shown) | |||
| Line 1: | Line 1: | ||
| − | + | These are the functions provided by the [[ARM9 BIOS]]. Names starting with <code>SVC_</code> are official, while others are guesses. | |
| − | |||
| − | These are the functions provided by the ARM9 BIOS. | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
! ID | ! ID | ||
| − | ! Name | + | ! Name/Prototype |
! Args | ! Args | ||
! Changes | ! Changes | ||
| Line 33: | Line 31: | ||
| swiIntrWait | | swiIntrWait | ||
| ?? | | ?? | ||
| − | | same as DS | + | | same as DS (but bugged? see note) |
|- | |- | ||
| 0x05 | | 0x05 | ||
| swiVBlankIntrWait | | swiVBlankIntrWait | ||
| ?? | | ?? | ||
| − | | same as DS | + | | same as DS (but bugged? see note) |
|- | |- | ||
| 0x06 | | 0x06 | ||
| Line 101: | Line 99: | ||
|- | |- | ||
| 0x13 | | 0x13 | ||
| − | | | + | | swiDecompressHuffmanWithCallbackWrite32bitUnits |
| ?? | | ?? | ||
| same as DS | | same as DS | ||
| Line 111: | Line 109: | ||
|- | |- | ||
| 0x15 | | 0x15 | ||
| − | | | + | | swiDecompressRLEwithCallbackWrite16bitUnits |
| ?? | | ?? | ||
| same as DS | | same as DS | ||
| Line 146: | Line 144: | ||
|- | |- | ||
| 0x20 | | 0x20 | ||
| − | | swiInit_crypto_heap | + | | swiInit_crypto_heap(Heap *heap, void *base, u32 len); |
| ?? | | ?? | ||
| '''new''' | | '''new''' | ||
| Line 166: | Line 164: | ||
|- | |- | ||
| 0x24 | | 0x24 | ||
| − | | | + | | SVC_SHA1Init(SVCSHA1Context *ctx) |
| ?? | | ?? | ||
| '''new''' | | '''new''' | ||
|- | |- | ||
| 0x25 | | 0x25 | ||
| − | | | + | | SVC_SHA1Update(SVCSHA1Context* ctx, const u8 *buf, u32 len) |
| ?? | | ?? | ||
| '''new''' | | '''new''' | ||
|- | |- | ||
| 0x26 | | 0x26 | ||
| − | | | + | | SVC_SHA1GetHash(SVCSHA1Context *ctx, u8 *hash) |
| ?? | | ?? | ||
| '''new''' | | '''new''' | ||
| Line 191: | Line 189: | ||
|- | |- | ||
| 0x29 | | 0x29 | ||
| − | | | + | | swiSHA1_Random |
| looks like it's trying to generate a random number using SHA1 | | looks like it's trying to generate a random number using SHA1 | ||
| '''new''' | | '''new''' | ||
| Line 215: | Line 213: | ||
| formerly jump to garbage | | formerly jump to garbage | ||
|} | |} | ||
| + | |||
| + | The two ignored function do return without doing anything (they are rejected before calling the SWI function table). The other unused functions do hang in an endless loop. | ||
| + | |||
| + | '''Note:''' swiHalt does correctly use CP15 to halt the ARM9 processor. But, swiVBlankIntrWait and swiIntrWait do use port 0x4000301 (which would be correct on ARM7, unknown if the same mechanism is actually supported on ARM9, if it isn't supported then the functions would more or less behave as desired - wait for IRQ flags to get set - but without actually switching the CPU into low-power mode). | ||
== See Also == | == See Also == | ||
* [[ARM7 BIOS]] | * [[ARM7 BIOS]] | ||
Latest revision as of 05:43, 7 October 2022
These are the functions provided by the ARM9 BIOS. Names starting with SVC_ are official, while others are guesses.
| ID | Name/Prototype | Args | Changes |
|---|---|---|---|
| 0x00 | N/A (hangs) | none | formerly SoftReset |
| 0x01 | swiDecompressLZSSwithCallbackWrite8bitUnits | ?? | formerly jump to 0 |
| 0x02 | swiDecompressLZSSwithCallbackWrite16bitUnits | ?? | formerly jump to 0 |
| 0x03 | swiWaitByLoop | ?? | same as DS |
| 0x04 | swiIntrWait | ?? | same as DS (but bugged? see note) |
| 0x05 | swiVBlankIntrWait | ?? | same as DS (but bugged? see note) |
| 0x06 | swiHalt | ?? | same as DS |
| 0x07-0x08 | N/A (hangs) | ?? | same as DS / formerly jump to 0 |
| 0x09 | swiDivide | ?? | same as DS |
| 0x0A | N/A (hangs) | ?? | same as DS / formerly jump to 0 |
| 0x0B | swiCopy | ?? | same as DS |
| 0x0C | swiFastCopy | ?? | same as DS |
| 0x0D | swiSqrt | ?? | same as DS |
| 0x0E | swiCRC16 | ?? | same as DS |
| 0x0F | N/A (hangs) | ?? | formerly IsDebugger |
| 0x10 | swiUnpackBits | ?? | same as DS |
| 0x11 | swiDecompressLZSSWram | ?? | same as DS |
| 0x12 | N/A (ignored) | ?? | (formerly swiDecompressLZSSVram) |
| 0x13 | swiDecompressHuffmanWithCallbackWrite32bitUnits | ?? | same as DS |
| 0x14 | swiDecompressRLEWram | ?? | same as DS |
| 0x15 | swiDecompressRLEwithCallbackWrite16bitUnits | ?? | same as DS |
| 0x16 | swiDecodeDelta8 | ?? | same as DS |
| 0x17 | N/A (hangs) | ?? | same as DS / formerly jump to 0 |
| 0x18 | swiDecodeDelta16 | ?? | same as DS |
| 0x19 | swiDecompressLZSSwithCallbackWrite16bitUnits | ?? | same as SWI 0x02 / formerly jump to 0 |
| 0x1A-0x1E | N/A (hangs) | ?? | same as DS / formerly jump to 0 |
| 0x1F | swiCustomPost | ?? | same as DS |
| 0x20 | swiInit_crypto_heap(Heap *heap, void *base, u32 len); | ?? | new |
| 0x21 | swiRSA_decrypt | ?? | new |
| 0x22 | swiRSA_decrypt_signature | ?? | new |
| 0x23 | swiRSA_decrypt_der | ?? | new |
| 0x24 | SVC_SHA1Init(SVCSHA1Context *ctx) | ?? | new |
| 0x25 | SVC_SHA1Update(SVCSHA1Context* ctx, const u8 *buf, u32 len) | ?? | new |
| 0x26 | SVC_SHA1GetHash(SVCSHA1Context *ctx, u8 *hash) | ?? | new |
| 0x27 | swiSHA1 | ?? | new |
| 0x28 | swiSHA1_Compare | ?? | new |
| 0x29 | swiSHA1_Random | looks like it's trying to generate a random number using SHA1 | new |
| 0x2A | N/A (hangs) | ?? | formerly jump to garbage |
| 0x2B | N/A (ignored) | ?? | formerly jump to garbage |
| 0x2C-0x3F | N/A (hangs) | ?? | formerly jump to garbage |
| 0x40-0xFF | Mirrors of 0x00-0x3F | ?? | formerly jump to garbage |
The two ignored function do return without doing anything (they are rejected before calling the SWI function table). The other unused functions do hang in an endless loop.
Note: swiHalt does correctly use CP15 to halt the ARM9 processor. But, swiVBlankIntrWait and swiIntrWait do use port 0x4000301 (which would be correct on ARM7, unknown if the same mechanism is actually supported on ARM9, if it isn't supported then the functions would more or less behave as desired - wait for IRQ flags to get set - but without actually switching the CPU into low-power mode).